Hardware enhancements for improved performance of memory emulation method
First Claim
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1. An apparatus for testing, by memory emulation, a microprocessor-based unit under test (UUT) having a kernel formed by at least a microprocessor, a memory, an address bus and a data bus, said apparatus comprising:
- an emulation memory connectable to said UUT in substitution for said UUT memory during testing of said UUT;
means for reading data from said emulation memory under control of said UUT microprocessor; and
a buffer circuit, comprising (a) gated data buffer means coupled to at least one data bus line at a data input of said microprocessor,(b) gated status buffer means coupled to at least one external connection of said microprocessor for carrying a signal indicative of an operational status of said microprocessor and(c) synchronization signal generation means responsive to said signal on said at least one external connection of said microprocessor for generating a synchronization signal for controlling acceptance of signals by both said gated data buffer means and said gated status buffer means; and
output means for reading out data stored in said buffer circuit.
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Abstract
Addition of gated buffers which are accessible by the test apparatus microprocessor for receiving status information and the signals on some of the lines of the data bus of a microprocessor-based system under test provides the capacity for self testing, automatic calibration, improved diagnostics of a kernel at low levels of kernel operability and faster operation of the test system.
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Citations
12 Claims
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1. An apparatus for testing, by memory emulation, a microprocessor-based unit under test (UUT) having a kernel formed by at least a microprocessor, a memory, an address bus and a data bus, said apparatus comprising:
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an emulation memory connectable to said UUT in substitution for said UUT memory during testing of said UUT; means for reading data from said emulation memory under control of said UUT microprocessor; and a buffer circuit, comprising (a) gated data buffer means coupled to at least one data bus line at a data input of said microprocessor, (b) gated status buffer means coupled to at least one external connection of said microprocessor for carrying a signal indicative of an operational status of said microprocessor and (c) synchronization signal generation means responsive to said signal on said at least one external connection of said microprocessor for generating a synchronization signal for controlling acceptance of signals by both said gated data buffer means and said gated status buffer means; and output means for reading out data stored in said buffer circuit. - View Dependent Claims (2, 3, 4, 5)
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6. An arrangement for calibrating a memory evaluation test apparatus which tests a microprocessor-based unit under test (UUT) having a kernel formed by at least a microprocessor, a memory and a data bus and an address bus, said arrangement comprising:
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emulation memory means connectable to said UUT in substitution for said UUT memory during calibration of said testing apparatus, means for loading a selected bit pattern into a predetermined location in said emulation memory means, means for causing said microprocessor to access said preselected location of said emulation memory whereby said emulation memory is caused to place said preselected bit pattern on said data bus, synchronization signal generation means including means for comparing signal bits appearing on said data bus with bits of said preselected bit pattern and bus cycle counting means for counting bus cycles prior to when said comparison means detects a bit pattern on said data bus matching said bits of said preselected bit pattern, and means for producing a synchronization signal a number of bus cycles after further access of said emulation memory equal to the number of bus cycles counted by said counting means.
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7. A method for calibrating a memory emulation testing apparatus which tests a microprocessor-based systems having a kernel formed by at least a microprocessor, a memory and data and address busses, said method comprising the steps of:
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storing a predetermined bit pattern in an emulation memory, causing said microprocessor to command placement of said predetermined bit pattern on said data bus, counting bus cycles of said microprocessor subsequent to said causing step and prior to an appearance of said predetermined bit pattern on said data bus, and generating a synchronization signal a number of bus cycles after each microprocessor command equal to the number of bus cycles mounted in said counting step.
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8. Apparatus for testing, by memory emulation, a microprocessor-based unit under test (UUT) having a kernel formed by at least a microprocessor and a memory, comprising:
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an emulation memory for connection to said UUT in substitution for said UUT memory during testing of said UUT; first connection means for connecting said emulation memory to said system; second connection means for connecting said apparatus to at least one status pin and one data input pin of said microprocessor; means for reading data from said emulation memory under control of said UUT microprocessor; and a self-test circuit means, comprising; (a) a gated buffer circuit means including a gated data buffer circuit means and a gated status buffer circuit means, (b) connector means for connecting said first connection means and said second connection means to an input/output port of said apparatus, and (c) means for reading data stored in said gated buffer circuit means to self-test said apparatus.
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9. An adaptive synchronization signal generating circuit for use in a tester for microprocessor-based systems including a microprocessor, a memory and a memory access bus, said circuit including:
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means for causing a predetermined bit pattern to be read from said memory and placed on said memory access but at a predetermined time, means for monitoring said memory access bus to detect an occurrence of said predetermined bit pattern, means for counting processing cycles of said microprocessor between said predetermined time and detection of said predetermined bit pattern by said means for monitoring said memory access bus, and means for storing a count produced by said means for counting processing cycles of said microprocessor. - View Dependent Claims (10)
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11. An adaptive synchronization signal generating method for use in a tester for microprocessor-based systems including a microprocessor, a memory and a memory access bus, including the steps of:
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causing a predetermined bit pattern to be read from said memory and placed on said memory access bus at a predetermined time, monitoring said memory access bus to detect an occurrence of said predetermined bit pattern, counting processing cycles of said microprocessor between said predetermined time and detection of said predetermined bit pattern, and storing said count of processing cycles of said microprocessor between said predetermined time and detection of said predetermined bit pattern. - View Dependent Claims (12)
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Specification