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Hardware enhancements for improved performance of memory emulation method

  • US 5,068,852 A
  • Filed: 11/24/1989
  • Issued: 11/26/1991
  • Est. Priority Date: 11/23/1989
  • Status: Expired due to Fees
First Claim
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1. An apparatus for testing, by memory emulation, a microprocessor-based unit under test (UUT) having a kernel formed by at least a microprocessor, a memory, an address bus and a data bus, said apparatus comprising:

  • an emulation memory connectable to said UUT in substitution for said UUT memory during testing of said UUT;

    means for reading data from said emulation memory under control of said UUT microprocessor; and

    a buffer circuit, comprising (a) gated data buffer means coupled to at least one data bus line at a data input of said microprocessor,(b) gated status buffer means coupled to at least one external connection of said microprocessor for carrying a signal indicative of an operational status of said microprocessor and(c) synchronization signal generation means responsive to said signal on said at least one external connection of said microprocessor for generating a synchronization signal for controlling acceptance of signals by both said gated data buffer means and said gated status buffer means; and

    output means for reading out data stored in said buffer circuit.

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