Hardware enhancements for improved performance of memory emulation method

• US 5,068,852 A
• Filed: 11/24/1989
• Issued: 11/26/1991
• Est. Priority Date: 11/23/1989
• Status: Expired due to Fees

• Current Assignee: John Fluke Mfg. Co., Inc. (Fortive Corp.)
• Original Assignee: John Fluke Mfg. Co., Inc. (Fortive Corp.)
• Inventors: Locke, Thomas P.
• Primary Examiner(s): Atkinson, Charles E.
• Assistant Examiner(s): CHUNG, PHUNG M
• Application Number:
  US07/441,094
• Time in Patent Office: 732 Days
• Field of Search: 371/16.2, 371/5.1, 371/16.1, 371/19
• US Class Current: 714/29
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

Addition of gated buffers which are accessible by the test apparatus microprocessor for receiving status information and the signals on some of the lines of the data bus of a microprocessor-based system under test provides the capacity for self testing, automatic calibration, improved diagnostics of a kernel at low levels of kernel operability and faster operation of the test system.

Claims

1. An apparatus for testing, by memory emulation, a microprocessor-based unit under test (UUT) having a kernel formed by at least a microprocessor, a memory, an address bus and a data bus, said apparatus comprising:

an emulation memory connectable to said UUT in substitution for said UUT memory during testing of said UUT;

means for reading data from said emulation memory under control of said UUT microprocessor; and

a buffer circuit, comprising (a) gated data buffer means coupled to at least one data bus line at a data input of said microprocessor,

(b) gated status buffer means coupled to at least one external connection of said microprocessor for carrying a signal indicative of an operational status of said microprocessor and

(c) synchronization signal generation means responsive to said signal on said at least one external connection of said microprocessor for generating a synchronization signal for controlling acceptance of signals by both said gated data buffer means and said gated status buffer means; and

output means for reading out data stored in said buffer circuit.

2. The apparatus according to claim 1, wherein

said gated data buffer means and said gated status buffer means are coupled to said microprocessor by coupling means including respective conductor means in a common cable.

3. The apparatus according to claim 2, wherein

said coupling means includes a respective buffer means for each said conductor means.

4. The apparatus according to claim 3, further including

a test system evaluation means for evaluating signals captured by said test apparatus and wherein

said output means includes means for coupling at least said gated data buffer means to an input of said test system evaluation means.

5. The apparatus according to claim 4, wherein said test system evaluation means is a microprocessor.

6. An arrangement for calibrating a memory evaluation test apparatus which tests a microprocessor-based unit under test (UUT) having a kernel formed by at least a microprocessor, a memory and a data bus and an address bus, said arrangement comprising:

emulation memory means connectable to said UUT in substitution for said UUT memory during calibration of said testing apparatus,

means for loading a selected bit pattern into a predetermined location in said emulation memory means,

means for causing said microprocessor to access said preselected location of said emulation memory whereby said emulation memory is caused to place said preselected bit pattern on said data bus,

synchronization signal generation means including means for comparing signal bits appearing on said data bus with bits of said preselected bit pattern and bus cycle counting means for counting bus cycles prior to when said comparison means detects a bit pattern on said data bus matching said bits of said preselected bit pattern, and

means for producing a synchronization signal a number of bus cycles after further access of said emulation memory equal to the number of bus cycles counted by said counting means.

7. A method for calibrating a memory emulation testing apparatus which tests a microprocessor-based systems having a kernel formed by at least a microprocessor, a memory and data and address busses, said method comprising the steps of:

storing a predetermined bit pattern in an emulation memory,

causing said microprocessor to command placement of said predetermined bit pattern on said data bus,

counting bus cycles of said microprocessor subsequent to said causing step and prior to an appearance of said predetermined bit pattern on said data bus, and

generating a synchronization signal a number of bus cycles after each microprocessor command equal to the number of bus cycles mounted in said counting step.

8. Apparatus for testing, by memory emulation, a microprocessor-based unit under test (UUT) having a kernel formed by at least a microprocessor and a memory, comprising:

an emulation memory for connection to said UUT in substitution for said UUT memory during testing of said UUT;

first connection means for connecting said emulation memory to said system;

second connection means for connecting said apparatus to at least one status pin and one data input pin of said microprocessor;

means for reading data from said emulation memory under control of said UUT microprocessor; and

a self-test circuit means, comprising;

(a) a gated buffer circuit means including a gated data buffer circuit means and a gated status buffer circuit means,

(b) connector means for connecting said first connection means and said second connection means to an input/output port of said apparatus, and

(c) means for reading data stored in said gated buffer circuit means to self-test said apparatus.

9. An adaptive synchronization signal generating circuit for use in a tester for microprocessor-based systems including a microprocessor, a memory and a memory access bus, said circuit including:

means for causing a predetermined bit pattern to be read from said memory and placed on said memory access but at a predetermined time,

means for monitoring said memory access bus to detect an occurrence of said predetermined bit pattern,

means for counting processing cycles of said microprocessor between said predetermined time and detection of said predetermined bit pattern by said means for monitoring said memory access bus, and

means for storing a count produced by said means for counting processing cycles of said microprocessor.

10. An adaptive synchronization signal generating circuit for use in a tester for microprocessor-based system as recited in claim 9, further including:

means for causing a second predetermined bit pattern to be read from said memory and placed on said memory access but at a predetermined time, and

means for updating storage by said means for storing of said processing cycle count by said means for counting processing cycles of said microprocessor based on a count of processing cycles between said second predetermined bit pattern being read from said memory and detection of said second predetermined bit pattern on said memory access bus.

11. An adaptive synchronization signal generating method for use in a tester for microprocessor-based systems including a microprocessor, a memory and a memory access bus, including the steps of:

causing a predetermined bit pattern to be read from said memory and placed on said memory access bus at a predetermined time,

monitoring said memory access bus to detect an occurrence of said predetermined bit pattern,

counting processing cycles of said microprocessor between said predetermined time and detection of said predetermined bit pattern, and

storing said count of processing cycles of said microprocessor between said predetermined time and detection of said predetermined bit pattern.

12. An adaptive synchronization signal generating method for use in a tester for microprocessor-based systems as recited in claim 11, further including steps of

causing a second predetermined bit pattern to be read from said memory and placed on said memory access bus at a predetermined time, and

updating storage of said processing cycle count based on a count of processing cycles between said second predetermined bit pattern being read from said memory and detection of said second predetermined bit pattern on said memory access bus.