Process of making a ferroelectric electronic component and product

• US 5,070,026 A
• Filed: 06/26/1989
• Issued: 12/03/1991
• Est. Priority Date: 06/26/1989
• Status: Expired due to Fees

• Current Assignee: Spire Corporation
• Original Assignee: Spire Corporation
• Inventors: Buchanan, Bobby L., Greenwald, Anton C.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Griffis, Andrew
• Application Number:
  US07/371,548
• Time in Patent Office: 890 Days
• Field of Search: 29/830-832, 29/841, 437/51, 437/DIG. 915, 437/3, 437/52, 357/67, 357/25, 357/29, 357/30
• US Class Current: 438/3
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

An improved process of making a ferroelectric electronic component, such as a non-volatile RAM or an electro-optic switching array, is disclosed. The process essentially includes the separate formation of two subassemblies and then connecting them by placing one on top of the other. Electrical contacts are made by "bumping" or other "flip chip" techniques.

Claims

1. An MOCVD process of making a nonvolatile random access memory component comprising:

(a) forming by MOCVD a first subassembly on a first substrate;

(b) depositing by MOCVD a smooth conductive layer of a noble metal on said first substrate;

(c) depositing by MOCVD a ferroelectric material on said smooth conductive layer;

(d) forming MOCVD a second subassembly on a second substrate, said first substrate and said second substrate being formed of the same material;

(e) depositing by MOCVD an integrated circuit on said second substrate;

(f) forming a plurality of electrical contacts on said integrated circuit; and

(c) connecting said two subassemblies by placing one on top of the other such that said electrical contacts abut said layer of ferroelectric material.

2. The process of claim 1 wherein said substrate material is one of a group consisting of silicon, gallium arsenide, and sapphire.

3. The process of claim 1 wherein said layer of ferroelectric material is one of a group consisting of PZT, PZLT, and lead-germanate.

4. The process of claim 1 wherein said smooth conductive layer is characterized by a crystal lattice structure and a thermal coefficient compatible with said ferroelectric material to enable its MOCVD deposition on said first substrate.

5. The process of claim 4 wherein said conductive layer is one of a group consisting of noble metals, gold and platinum, and conductive oxides, SnO₂ and InSnO₂.

6. The process of claim 1 wherein said electrical contacts provided on said integrated circuit are formed of indium or gold.

7. A process of making an optoelectronic switching array comprising:

(a) providing a first GaAs substrate;

(b) forming by sputtering a conductive layer on said first substrate;

(c) forming by sputtering a layer of ferroelectric material on said conductive layer;

(d) providing a second GaAs substrate;

(e) forming by sputtering an integrated circuit on said second GaAs substrate;

(f) forming a plurality of electrical contacts on said integrated circuit; and

(g) connecting the two subassemblies respectively formed on each of said first and second GaAs substrates by placing one on top of the other so that said plurality of electrical contacts abut said layer of ferroelectric material.

8. The process of claim 7 wherein said first and second GaAs substrates are first polished and cleaned by chemical solutions in ultrasonic baths, followed by sputter etching the surfaces of said substrates.

9. The process of claim 7 wherein said plurality of electrical contacts on said integrated circuit are formed by tape automated bonding.

10. The process of claim 7 wherein said layer of ferroelectric material is one of a group consisting of PZT and PLZT, and lead-germanate and, wherein said conductive layer is one of a group consisting of noble metals, gold and platinum, and conductive oxides, SnO₂ and InSnO₂.

11. The process of claim 7 wherein said plurality of electrical contacts on said integrated circuit are formed by flip chip bonding.