Method of making dense flash EEprom semiconductor memory structures
First Claim
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1. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
- forming a first plurality of continuous elongated parallel strips of conductive material on said substrate in a manner to be insulated therefrom by a first dielectric layer,forming a second plurality of continuous elongated parallel strips of conductive material on said substrate and over said first plurality of conductive strips in a manner to be insulated therefrom by a second dielectric layer, said first and second plurality of strips having their lengths oriented substantially orthogonal to each other,thereafter forming spacers along opposing edges of adjacent ones of said second plurality of parallel strips and extending toward each other but leaving a defined space therebetween, andthereafter forming a gap in said first plurality of strips through the space defined by the spacers, thereby forming electrically isolated floating gates from said first plurality of strips.
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Abstract
An improved electrically erasable and programmable read only memory (EEprom) structure and processes of making it which results in a denser integrated circuit, improved operation and extended lifetime. In order to eliminate certain ill effects resulting from tolerances which must be allowed for registration of masks used in successive steps in forming the semiconductor structures, spacers are formed with reference to the position of existing elements in order to form floating gates and define small areas of these gates where, in a controlled fashion, a tunnel erase dielectric is formed. Alternatively, a polysilicon strip conductor is separated into separate control gates by a series of etching steps that includes an anisotropic etch of boundary oxide layers to define the area of the control gates that are coupled to the erase gate through an erase dielectric. In either case, the polysilicon layer strip can alternatively be separated by growing oxide thereon until it is completely consumed. A technique for forming a pure oxide dielectric layer of uniform thickness includes depositing a thin layer of an undoped polysilicon material and then oxidizing its surface until substantially the entire undoped polysilicon layer is consumed and made part of the resulting oxide layer. Overlapping doped regions are provided in the substrate by an ion implantation mask that adds spacers to the mask aperture to change its size between implants.
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Citations
30 Claims
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1. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming a first plurality of continuous elongated parallel strips of conductive material on said substrate in a manner to be insulated therefrom by a first dielectric layer, forming a second plurality of continuous elongated parallel strips of conductive material on said substrate and over said first plurality of conductive strips in a manner to be insulated therefrom by a second dielectric layer, said first and second plurality of strips having their lengths oriented substantially orthogonal to each other, thereafter forming spacers along opposing edges of adjacent ones of said second plurality of parallel strips and extending toward each other but leaving a defined space therebetween, and thereafter forming a gap in said first plurality of strips through the space defined by the spacers, thereby forming electrically isolated floating gates from said first plurality of strips. - View Dependent Claims (2, 3, 4, 5, 6, 30)
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7. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming a first plurality of continuous elongated parallel strips of conductive material on said substrate in a manner to be insulated therefrom by a first dielectric layer, including depositing doped polysilicon by low pressure chemical vapor deposition at a temperature in excess of 620 degrees centigrade, forming a second plurality of continuous elongated parallel strips of conductive material on said substrate and over said first plurality of conductive strips in a manner to be insulated therefrom by a second dielectric layer, said first and second plurality of strips having their lengths oriented substantially orthogonal to each other, wherein the step of forming the second plurality of elongated strips includes depositing doped polysilicon by low pressure chemical vapor deposition at a temperature less than 600 degrees centigrade, thereafter forming spacers along opposing edges of adjacent ones of said second plurality of parallel strips and extending toward each other but leaving a defined space therebetween, and thereafter performing an operation on said first plurality of strips through the space defined by the spacers.
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8. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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(a) implanting dopant of opposite polarity in adjacent regions of a semiconductor substrate, by a method comprising the steps of; forming a first masking layer over said substrate which has a plurality of apertures therein, providing a second mask over said first masking layer in a manner to cover a portion of said apertures from one side thereof, thereby leaving a first restricted opening to said substrate adjacent an opposite side of said apertures, performing a first implant of impurities of a first polarity through said first restricted opening, removing said second mask while maintaining said first masking layer in place, forming a spacer within said apertures at least along said opposite side thereof, thereby forming a second restricted opening therethrough, and providing a second implant of a second polarity opposite to said first polarity through said second restricted opening, whereby said spacer protects the surface of said semiconductor substrate which is implanted with impurities of the first polarity from over compensation from the second implant of said opposite polarity, (b) thereafter forming a first plurality of continuous elongated parallel strips of conductive material on said substrate in a manner to be insulated therefrom by a first dielectric layer, (c) thereafter forming a second plurality of continuous elongated parallel strips of conductive material on said substrate and over said first plurality of conductive strips in a manner to be insulated therefrom by a second dielectric layer, said first and second plurality of strips having their lengths oriented substantially orthogonal to each other, (d) thereafter forming spacers along opposing edges of adjacent ones of said second plurality of parallel strips and extending toward each other but leaving a defined space therebetween, and (e) thereafter performing an operation on said first plurality of strips through the space defined by the spacers.
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9. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming a first plurality of elongated parallel strips of conductive material on said substrate in a manner to be insulated therefrom by a first dielectric layer, forming a second plurality of elongated parallel strips of conductive material on said substrate and over said first plurality of conductive strips in a manner to be insulated therefrom by a second dielectric layer, said first and second plurality of strips having their lengths oriented substantially orthogonal to each other, thereby to form control gates, forming spacers of dielectric material along opposing edges of said control gates and extending toward each other with a gap of a predetermined width remaining therebetween that exposes portions of said first plurality of strips therein, etching away said exposed portions of said first plurality of strips, thereby forming isolated floating gates extending between etched spaces therebetween, thereafter reducing the size of the spacers in a manner to expand said gap, thereby exposing surface area portions of said floating gates adjacent said spacers, forming a third dielectric layer over the exposed surface area of the floating gates, and forming a third plurality of elongated parallel strips of conductive material across said third dielectric, thereby to form erase gates. - View Dependent Claims (12, 15)
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10. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming a first plurality of elongated parallel strips of conductive material on said substrate in a manner to be insulated therefrom by a first dielectric layer, forming a second plurality of elongated parallel strips of conductive material on said substrate and over said first plurality of conductive strips in a manner to be insulated therefrom by a second dielectric layer, said first and second plurality of strips having their lengths oriented substantially orthogonal to each other, thereby to form control gates, forming spacers of dielectric material along opposing edges of said control gates and extending toward each other with a gap of a predetermined width remaining therebetween that exposes portions of said first plurality of strips therein, said spacer forming step including forming first and second spacer portions in time sequence adjacent each other, the material of said first spacer portion exhibiting a significantly slower response to a given etching process than the material of said second spacer portion, etching away said exposed portions of said first plurality of strips, thereby forming isolated floating gates extending between etched spaces therebetween, thereafter reducing the size of the spacers in a manner to expand said gap, thereby exposing surface area portions of said floating gates adjacent said spacers, said spacer reducing step including the step of removing said second spacer portion by said given etching process, forming a third dielectric layer over the exposed surface area of the floating gates, and forming a third plurality of elongated parallel strips of conductive material across said third dielectric, thereby to form erase gates. - View Dependent Claims (11)
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13. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming a first plurality of elongated parallel strips of conductive material on said substrate in a manner to be insulated therefrom by a first dielectric layer, forming a second plurality of elongated parallel strips of conductive material on said substrate and over said first plurality of conductive strips in a manner to be insulated therefrom by a second dielectric layer, said first and second plurality of strips having their lengths oriented substantially orthogonal to each other, thereby to form control gates, forming spacers of dielectric material along opposing edges of said control gates and extending toward each other with a gap of a predetermined width remaining therebetween that exposes portions of said first plurality of strips therein, etching away said exposed portions of said first plurality of strips, thereby forming isolated floating gates extending between etched spaces therebetween, thereafter reducing the size of the spacers in a manner to expand said gap, thereby exposing surface area portions of said floating gates adjacent said spacers, forming a third dielectric layer over the exposed surface area of the floating gates, forming a third plurality of elongated parallel strips of conductive material across said third dielectric, thereby to form erase gates, and forming a fourth layer of dielectric over the control gates before the erase gates are formed, thereby isolating said control and erase gates. - View Dependent Claims (14)
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16. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming a first plurality of elongated parallel strips of conductive material on said substrate in a manner to be insulated therefrom by a first dielectric layer, including depositing doped polysilicon by low pressure chemical vapor deposition at a temperature in excess of 620 degrees centigrade, forming a second plurality of elongated parallel strips of conductive material on said substrate and over said first plurality of conductive strips in a manner to be insulated therefrom by a second dielectric layer, said first and second plurality of strips having their lengths oriented substantially orthogonal to each other, thereby to form control gates, wherein the step of forming the second plurality of elongated strips includes depositing doped polysilicon by low pressure chemical vapor deposition at a temperature less than 600 degrees centigrade, forming spacers of dielectric material along opposing edges of said control gates and extending toward each other with a gap of a predetermined width remaining therebetween that exposes portions of said first plurality of strips therein, etching away said exposed portions of said first plurality of strips, thereby forming isolated floating gates extending between etched spaces therebetween, thereafter reducing the size of the spacers in a manner to expand said gap, thereby exposing surface area portions of said floating gates adjacent said spacers, forming a third dielectric layer over the exposes surface area of the floating gates, and forming a third plurality of elongated parallel strips of conductive material across said third dielectric, thereby to form erase gates.
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17. A method of forming a plurality of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming a first layer of doped polysilicon conductive material across two adjacent of said memory cells and insulated from said substrate by first dielectric layer, forming a second dielectric layer over said first polysilicon layer, forming a second layer of doped polysilicon conductive material as a control gate over each of said adjacent memory cells, forming a third dielectric layer across said control gate and exposed portions of said second dielectric layer therebetween, forming a mask over said third dielectric layer with an aperture therein positioned between the adjacent cells but over the first polysilicon layer extending therebetween, removing the third dielectric layer and said first doped polysilicon layer under the aperture of said photoresist mask by subjecting them to an anisotropic etch, thereby separating the first doped polysilicon layer into a separate floating gate for each of said at least two adjacent cells and to leave a well in the structure under said aperture, thereafter partially etching said third dielectric layer exposed through said photoresist mask aperture by an isotropic etch, thereby moving vertical dielectric walls away from the region under said photoresist aperture to leave edges of the separated first doped polysilicon layer extending beyond said vertical dielectric walls and into said well, stripping said mask from said third dielectric layer, forming a fourth dielectric layer over the exposed polysilicon floating gates in said well, and forming an erase gate in said well in a manner that the fourth dielectric layer separates said erase gate from each of the separated first polysilicon layer floating gates. - View Dependent Claims (18, 19, 20)
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21. A method of forming a plurality of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming a first layer of doped polysilicon conductive material across two adjacent of said memory cells and insulated from said substrate by first dielectric layer, forming a second dielectric layer over said first polysilicon layer, forming a second layer of doped polysilicon conductive material as a control gate over each of said adjacent memory cells, forming a third dielectric layer across said control gate and exposed portions of said second dielectric layer therebetween, forming a mask over said third dielectric layer with an aperture therein positioned between the adjacent cells but over the first polysilicon layer extending therebetween, removing the third dielectric layer under the aperture of said photoresist mask, thereby exposing said first polysilicon layer, growing oxide through the mask aperture on the first polysilicon layer in a manner that the first polysilicon layer is completely consumed, thereby separating the first doped polysilicon layer into a separate floating gate for each of said at least two adjacent cells, and forming an erase gate through said mask aperture.
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22. A method of forming a layer of oxide on a doped polysilicon conductor that is an electrically isolated floating gate provided as part of an integrated circuit, including the steps of:
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forming a layer of an undoped polysilicon material on said doped polysilicon surface, thereafter growing a layer of oxide on the undoped polysilicon material layer for a time until substantially the entire undoped polysilicon material layer has been consumed and made part of the grown oxide layer, and forming a conductive erase gate over at least a portion of said grown oxide layer.
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23. A method of forming an array of memory cells on a semiconductor substrate, comprising:
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forming a thin layer of gate oxide insulating material across said substrate, forming a first set of substantially parallel strips of doped polysilicon material across said oxide in order to form a first set of elongated electrically conductive strips thereacross, thereafter forming a layer of undoped polysilicon material extending over top surfaces of said gate oxide and said doped polysilicon material strips, thereafter growing a layer of oxide on the undoped polysilicon material layer for a time until substantially the entire undoped polysilicon material layer has been consumed and made part of the grown oxide layer, thereafter forming a second set of substantially parallel strips of doped polysilicon material across said layer of grown oxide in order to form a second set of elongated electrically conductive strips thereacross, said first and second sets of conductive strips having their lengths oriented substantially orthogonal to each other, and thereafter removing portions of said first set of conductive strips between said second set of conductive strips, thereby forming a plurality of electrically isolated gates along the length of each of said first set of conductive strips.
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24. A method of forming an electrically erasable and programmable read only memory having a doped polysilicon floating gate separate from a semiconductor substrate and from a doped polysilicon control gate by oxide insulating layers, and an erase gate separated from a portion of said floating gate by an erase oxide, comprising the steps of:
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depositing said floating gate polysilicon layer in excess of 620°
C.,growing said erase gate oxide over a portion of the surface of said floating gate polysilicon layer, depositing said control gate polysilicon layer by a temperature of less than 600°
C.,growing an insulating oxide layer over said control gate polysilicon layer, and forming a conductive erase gate in a position to be separated from said floating gate by said erase gate oxide and from said control gate by said insulating oxide layer.
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25. A method of implanting dopant of opposite conductivity type in adjacent regions of a semiconductor substrate, comprising the steps of:
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forming a first masking layer over said substrate which has a plurality of apertures therein, providing a second mask over said first masking layer in a manner to cover a portion of said apertures from one side thereof, thereby leaving a first restricted opening to said substrate adjacent an opposite side of said apertures, performing a first implant of impurities of a first polarity through said first restricted opening, removing said second mask while maintaining said first masking layer in place, forming a spacer within said apertures at least along said opposite side thereof, thereby forming a second restricted opening therethrough, and providing a second implant of a second polarity opposite to said first polarity through said second restricted opening, whereby said spacer protects the surface of said semiconductor substrate implanted with impurities of the first polarity from overcompensation from said second implant of the opposite second polarity. - View Dependent Claims (26)
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27. A method of forming an array of a plurality of memory cells on a semiconductor substrate, comprising the steps of:
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forming a doped polysilicon strip extending across at least two adjacent memory cells and insulated from said substrate by a thin insulating layer therebetween, protecting the polysilicon strip by a mask that leaves a portion thereof between said at least two cells exposed, and oxidizing said exposed doped polysilicon until the exposed portion is completely consumed by the oxidation process, thereby leaving electrically separate floating gates associated with each of said adjacent cells. - View Dependent Claims (28, 29)
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Specification
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Current AssigneeSanDisk Technologies LLC (Western Digital Corporation)
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Original AssigneeSunDisk Corporation (Seagate Technology Holdings Plc)
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InventorsHarari, Eliyahou, Yuan, Jack H.
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Primary Examiner(s)Hearn, Brian E.
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Assistant Examiner(s)CHAUDHARI, CHANDRA P
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Application NumberUS07/323,779Time in Patent Office993 DaysField of Search437/43, 437/52, 437/195, 437/968, 437/983, 437/193, 357/23.5US Class Current438/267CPC Class CodesH10B 41/00 Electrically erasable-and-p...H10B 41/10 characterised by the top-vi...H10B 69/00 Erasable-and-programmable R...
