Full wafer integrated circuit testing device

• US 5,070,297 A
• Filed: 06/04/1990
• Issued: 12/03/1991
• Est. Priority Date: 06/04/1990
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hashimoto, Masashi, Kwon, Oh-Kyong, Malhi, Satwinder, Born, Eng C.
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): Nguyen, Vinh P.
• Application Number:
  US07/532,481
• Time in Patent Office: 547 Days
• Field of Search: 324/72.5, 324/158 P, 324/158 F, 324/158 R, 324/73.1, 437/8, 439/482, 371/25.1, 371/15.1
• US Class Current: 324/754.03
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory

Abstract

A full wafer integrated circuit testing device (10) tests integrated circuits (15) formed as a wafer in conjunction with a test control unit (40). Probe units (14) associate with respective integrated circuits (15). Probe tips (16) on probe units (14) communicate with respective pads (19) with the integrated circuits (15). Interface circuitry (36) selectively communicates test data between the test control unit (40) and the integrated circuit (15). Test pins (16) have positions on probe units (14) associated with respective integrated circuit connection points (19) for testing associated integrated circuit (15) components. Interface circuitry (36) includes comparators (54 and 56) that compare signals between the integrated circuit (15) and the test control unit (40). Memory components (66 and 68) store data associated with signals from test control unit (40) and said integrated circuit (15). Compliant material (32) assures that probe tips (16) throughout probe card (10) positively and conductively engage integrated circuit pads (19) of all associated integrated circuits (15) of a wafer.

Claims

1. An integrated circuit testing device simultaneously connected to a plurality of subject integrated circuits for testing substantially all of said plurality of subject integrated circuits formed on a semiconductor wafer, said testing device connected to and operating in conjunction with a test control unit, said testing device comprising:

a support wafer;

a plurality of probe units formed on said support wafer, each one of said plurality of probe units for testing respective ones of said plurality of subject integrated circuits and comprising a plurality of probe tips operable to communicate with respective nodes associated with a respective subject integrated circuit; and

at least one active interface cirucuit formed on said support wafer and connected between said test control unit and said probe units for selectively controlling data transmitted between the test control unit and the subject integrated circuits.

2. The device of claim 1, wherein each of said probe tips on each of said probe units connects in parallel with an associated probe tip on another probe units, each of said probe tips capable of receiving in parallel a test signal from the test control unit.

3. The device of claim 1, wherein said active interface circuit further comprises at least one amplifier for communicating and amplifying signals between the subject integrated circuit and the test control unit.

4. The device of claim 1, wherein said active interface circuit further comprises at least one comparator for generating an output by comparing signals between the subject integrated circuit and the test control unit.

5. The device of claim 1, wherein said active interface circuit further comprises at least one memory component associated with said probe units for storing data associated with signals from said test control unit and said integrated circuit.

6. The device of claim 5, wherein said active interface circuit comprises at least one comparator for generating an output by comparing signals between the subject interface circuit and the test control unit, and wherein said memory component further comprise storage capability for storing said comparator output.

7. The device of claim 5, wherein said memory component further connects to an output bus for communicating an output between said active interface circuit and the test control unit.

8. The device of claim 7, wherein said output bus further comprises circuitry for communicating an output from said memory components and the test control unit.

9. The device of claim 1, further comprising a power bus for providing test power to the subject integrated circuit.

10. An integrated circuit testing device simultaneously connected to a plurality of subject integrated circuits for testing substantially all of a plurality of subject integrated circuits formed on a semiconductor wafer, said testing device connected to and operating in conjunction with a test control unit, said testing device comprising:

a support wafer;

a plurality of probe units formed on the support wafer by integrated circuit fabrication processes, each one of said plurality of probe units for testing respective ones of said plurality of subject integrated circuits and comprising a plurality of probe tips integrally mounted to said probe units and operable to communicate with respective nodes associated with a respective integrated circuit; and

at least one active interface circuit formed within the wafer and connected between said test control unit and said probe unit for selectively processing data transmitted between the test control unit and the subject integrated circuits.

11. The integrated circuit testing device of claim 10, wherein the support wafer includes a silicon substrate for forming said active interface circuit.

12. The integrated circuit testing device of claim 11, further comprising an insulating layer affixed to said silicon substrate and said active interface circuit and a compliant material over said insulating layer, said compliant material assuring that said probe tips positively and conductively engage associated subject integrated circuits pads.

13. The integrated circuit testing device of claim 12, further comprising a plurality of metal contacts imbedded within said compliant material and penetrating said insulating layer to communicate with said active interface circuit.

14. The integrated circuit testing device of claim 13, further comprising a plurality of probe tips wherein each of said probe tips are mounted to one of said plurality of metal contacts for contacting nodes of the subject integrated circuit.

15. The integrated circuit testing device of claim 14, wherein each of said probe tips further comprises a metal bump connected to said metal contact for making electrical contact with the subject integrated circuit.

16. The integrated circuit testing device of claim 15, wherein said metal bump further comprises a pointed tip affixed to said metal bump, said pointed tip comprising a hard conductive material to assure conductive contact between said probe unit and the integrated circuit.

17. The integrated circuit testing device of claim 10, wherein said active interface circuit further comprising communication circuitry for communicating signals between the subject integrated circuit and the test control unit and a memory for storing signals from the subject integrated circuit.

18. The integrated circuit testing device of claim 17, wherein said active interface circuit comprises comparator circuitry connected to said communication circuitry for comparing a plurality of signal outputs from the subject integrated circuit to expected outputs and address circuitry for identifying the origin of said signal outputs.

19. The integrated circuit testing device of claim 17, wherein said active interface circuit includes failed subject integrated circuit component circuitry for providing data to the test control unit indicative of failed integrated circuit components.

20. The integrated circuit testing device in claim 17, wherein said active interface circuit further comprises failed subject integrated circuit circuitry for responding to a failed integrated circuit signal from the test control unit.

21. The integrated circuit testing device of claim 17, wherein said active interface circuit further includes a power bus switch connected to a power bus for providing power to the subject integrated circuit.

22. The integrated circuit testing device of claim 21, wherein said active interface circuit further comprises failed integrated circuit circuitry for responding to a failed subject integrated circuit signal from the test control unit and wherein said power bus switch further connects to said failed circuitry for turning off power to the subject integrated circuit in the event said failed circuitry receives a failed signal.

23. The integrated circuit testing device of claim 17, further comprising a ground bus connected to the subject integrated circuit and the test control unit for providing a reference voltage level for input and output signals.

24. An integrated circuit testing system for testing substantially all integrated circuits on a single semiconductor wafer, comprising:

a test control unit for generating and receiving test signals;

an integrated circuit testing device simultaneously connected to a plurality of subject integrated circuits for testing substantially all of said subject integrated circuits formed on a wafer, said testing device connected to and operating in conjunction with said test control unit, said integrated circuit test device comprising;

a support wafer;

a plurality of probe units formed on said support wafer, each one of said plurality of probe units for testing respective ones of said plurality of subject integrated circuits and comprising a plurality of probe tips operable to communicate with respective nodes associated with a respective integrated circuit; and

at least one active interface circuit formed on said support wafer and connected between said test control unit and a probe unit for selectively controlling data transmitted between the test control unit and the subject integrated circuits.

25. A method of integrated circuit testing for testing substantially all of a plurality of subject integrated circuits formed as a wafer in conjunction with a test control unit, comprising:

communicating between nodes associated with each of the subject integrated circuits and a plurality of probe units formed on a support wafer, said probe units associated with each of the respective integrated circuits; and

selectively controlling the transmission of data between the test control unit and the subject integrated circuits.

26. The method of claim 25, wherein said controlling step further comprises the step of using a plurality of test pins on said probe units to test associated subject integrated circuit components.

27. The method of claim 26, wherein said step of using test pins further comprises the step of connecting those test pins on at least two of said probe units selected to perform the same test in parallel.

28. The method of claim 25, wherein said selective controlling step further comprises the steps of amplifying and repeating signals between the subject integrated circuits and the test control unit.

29. The method of claim 25, wherein said selective controlling step further comprises the step of generating an output by comparing signals between the subject integrated circuit and the test control unit.

30. The method of claim 25, wherein said selective controlling step further comprises the step of storing data associated with signals from the test control unit and the subject integrated circuit.

31. The method of claim 30, wherein said selectively controlling step further comprises the step of generating an output by comparing signals between the test control unit and the subject integrated circuit and wherein said data storing step further comprises the step of storing said comparator output.

32. The method of claim 30, wherein said selective controlling step further comprises the step of communicating stored data to the test control unit.