Programmable memory matrix employing voltage-variable resistors

• US 5,070,383 A
• Filed: 01/10/1989
• Issued: 12/03/1991
• Est. Priority Date: 01/10/1989
• Status: Expired due to Term

• Current Assignee: Zoran Corporation (Qualcomm, Inc.)
• Original Assignee: Zoran Corporation (Qualcomm, Inc.)
• Inventors: Gerzberg, Levy, Shacham, Yosef Y., Sinar, Alexander B., Sirkin, Eric R., Blech, Ilan A.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US07/295,274
• Time in Patent Office: 1,057 Days
• Field of Search: 357/51, 357/45, 357/2
• US Class Current: 257/537
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: Y10S 257/91 Diode arrays, e.g. diode read-only memory array
• CPC Class Codes: Y10S 257/926 Elongated lead extending axially through another elongated lead

Abstract

A memory matrix comprises a plurality of word lines, a plurality of bit lines, and a stacked diode and voltage-variable resistor structure interconnecting bit lines to word lines. The stacked diode and voltage-variable resistor structure includes a doped region in a semiconductor substrate defining a work line, a doped polycrystalline silicon layer over said word line and forming a p-n junction therewith, and an amorphized region in the doped polycrystalline silicon layer having increased resistance over the non-amorphized portion of the doped polycrystalline silicon layer. A contact is made to the amorphized polycrystalline silicon material which preferably includes a titanium-tungsten barrier layer and an aluminum layer over the barrier layer. To improve the breakdown voltage of the diode structure, a region of opposite conductivity type is formed in the word line under the doped polycrystalline silicon layer either by out-diffusion of dopants from the polycrystalline silicon layer or by the implantation of dopant ions through the polycrystalline silicon layer into the word line.

Claims

1. A programmable memory array comprising

a monocrystalline semiconductor substrate,

a plurality of word lines formed in said substrate by dopants of a first conductivity type, and

a plurality of stacked diode and voltage-variable resistor structures on each word line with a bit contact to each stacked diode and voltage-variable resistor,

each diode comprising a doped polycrystalline layer of opposite conductivity type in contact with a word line and an ion-implanted region of opposite conductivity type in said word line thereby forming a p-n junction with said word line, and each voltage-variable resistor comprising an amorphized surface region in said polysilicon layer.

2. The programmable memory array as defined by claim 1 wherein each bit contact comprises a metal contact to said amorphized surface region.

3. The programmable memory array as defined by claim 2 wherein said metal contact comprises a barrier metal layer on said amorphized surface region and a second metal layer on said barrier metal layer.

4. A stacked diode and voltage-variable resistor structure comprising

a semiconductor substrate having a doped surface region of one conductivity type,

a layer of doped polycrystalline silicon on said doped surface region, said doped polycrystalline silicon being of opposite conductivity type,

an ion-implanted region of opposite conductivity type in said doped surface region underlying said doped polycrystalline silicon and forming a p-n junction with said doped surface region,

an amorphized region in said doped polycrystalline silicon layer having higher resistance than the non-amorphized doped polycrystalline silicon layer, and

a contact on said amorphized portion of said doped polycrystalline silicon layer.

5. The stacked diode and voltage-variable resistor structure as defined by claim 4 wherein said contact comprises a barrier metal layer on said amorphized region of said polycrystalline silicon layer and a layer of a second metal on said barrier metal layer.

6. The stacked diode and voltage-variable resistor structure as defined by claim 5 wherein said barrier metal comprises titanium-tungsten and said second metal comprises aluminum.