Forth specific language microprocessor

• US 5,070,451 A
• Filed: 04/10/1989
• Issued: 12/03/1991
• Est. Priority Date: 11/21/1984
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Moore, Charles H., Murphy, Robert W.
• Primary Examiner(s): Popek, Joseph A.
• Assistant Examiner(s): RUDOLPH, REBECCA
• Application Number:
  US07/336,632
• Time in Patent Office: 967 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/32
• CPC Class Codes: G06F 8/31 Programming languages or programming paradigms
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/321 Program or instruction counter, e.g. incrementing
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/4486 Formation of subprogram jump address

Abstract

A language specific microprocessor for the computer language known as FORTH is disclosed. The microprocessor includes four main registers each for holding a parameter; a L or instruction latch register for decoding instructions and activating microprocessor operation; an I or return index register for tracking returns; an N or next parameter register for operation with an arithmetic logic unit (ALU); and a T or top of parameter stack register with an appended ALU. A return stack port is connected to the I register and a parameter stack port is connected to the N register circuit, each have last in/first out (LIFO) memory stacks for reads and writes to isolated independent memory islands that are external to the microprocessor. The respective I, T and N registers are connected in respective series by paired bus connections for swapping parameters between adjacent registers. A first split 16 bit multiplexer J/K controls the LIFO stack for the I and N registers on paired 8 bit address stacks; a second 16 bit multiplexer designates the pointer to main memory with 65K addresses and an adjoining 65K for data. This addressing multiplexer receives selective input from a program counter P, the return index register I, the top of the parameter stack T and/or the instruction latch L. Movement to subroutine is handled in a single cycle with returns being handled at the end of any designated cycle. Asynchronous microprocessor operation is provided with the address multiplexer being simultaneously set up with an address to a future machine step, unloading from memory of appropriate data or instruction for the next machine step and asynchronously executing the current machine step. A two-phase clock latches data as valid on a rising edge and moves to a new memory location on a falling edge. This two phase clock is given a pulse width sufficient for all asynchronous cycles of microprocessor operations to settle. The microprocessor'"'"'s assembler language is FORTH and the stack and main memory port architecture uniquely complements FORTH to produce a small (17,000 gates) fast (40 mips) microprocess or operable on extant FORTH programs. Provision is made for an additional G port which enables the current operating state of the microprocesor to be mapped, addressing of up to 21 bits as well as the ability to operate the microprocessor in tandem with similar microprocessors.

Claims

1. A processor adapted to receive instructions and to execute multiple operations of a single instruction in parallel, comprising:

an instruction latch;

a main memory data port coupled to said instruction latch;

an instruction decode circuit for decoding an instruction in said instruction latch coupled to said instruction latch and having a plurality of control signal outputs;

a main memory address port coupled to a first one of said control signal outputs;

an arithmetic logic unit having a control input coupled to a second one of said control signal outputs and a first operand input;

an ALU multiplexer having an output coupled to said first operand input of said arithmetic logic unit, a first input coupled to said main memory data port via a first data path, and a select input coupled to a third one of said control signal outputs;

a top register coupled to an output of said arithmetic logic unit;

a next parameter register coupled to a second input of said ALU multiplexer via a second data path;

an index/return register coupled to a third input of said ALU multiplexer via a third data path;

a next parameter memory having a data I/O coupled to said next parameter register, said next parameter memory, next parameter register and top register forming a single parameter stack;

an index/return memory having a data I/O coupled to said index/return register for storing an index/return stack;

K stack pointer means having only a single pointer register for generating a pointer address for said next parameter memory having an output coupled to an address input of said next parameter memory and an input coupled to a fourth one of said control signal outputs; and

a J stack pointer circuit for generating a pointer address for said index/return memory having an output coupled to an address input of said index/return memory and an input coupled to a fifth one of said control signal outputs.

2. The processor of claim 1 further comprising an address multiplexer having an output coupled to said main memory address port, a first input coupled to said first one of said control signal outputs, a second input coupled to said top register, a third input coupled to said index/return register and a select input coupled to a sixth one of said control signals.

3. The processor of claim 1 further comprising a main memory multiplexer having an output coupled to said main memory data port and an input of said instruction latch, a first input coupled to said top register, a second input coupled to said next parameter register and a select input coupled to a sixth one of said control signals.

4. The processor of claim 1 wherein said ALU multiplexer further includes a fourth input coupled to said first one of said control signal outputs.

5. The processor of claim 1 further comprising a next parameter multiplexer having an output coupled to said next parameter register, a first input coupled to said top register, a second input coupled to said main memory data port and a select input coupled to a sixth one of said control signals.

6. The processor of claim 1 further comprising:

a program counter; and

an index/return multiplexer having an output coupled to said index/return register, a first input coupled to said top register, a second input coupled to an output of said program counter and a select input coupled to a sixth one of said control signal outputs.

7. The processor of claim 1 further comprising:

a fourth data path coupling an output of said top register to an input of said next parameter register;

a fifth data path coupling said output of said top register to an input of said index/return register;

whereby said arithmetic logic unit temporarily maintains an output value of said next parameter register while an output value of said top register is applied to an input of said next parameter register to enable a simultaneous, one clock cycle swap of the contents of top register and said next parameter register to be effected through said second and fourth data paths; and

whereby said arithmetic logic unit temporarily maintains an output value of said index/return register while an output of said top register is applied to an input of said index/return register to enable a simultaneous, one clock cycle swap of the contents of said top register and said index/return register to be effected through said third and fifth data paths.

8. The processor of claim 1 further comprising means, responsive to a predetermined bit of said instructions, for performing a subroutine return operation concurrently with other operations specified by said instructions.

9. The processor of claim 1 further comprising means, responsive to a predetermined bit of said instructions, for performing a subroutine call concurrently with other operations specified by said instructions.

10. The processor of claim 9 wherein said means for performing a subroutine call comprises means for storing a program count in said index/return register and providing an output of said instruction latch to said main memory address port.

11. The processor of claim 1 further comprising means for modifying a value in one of said registers by a multi-bit literal value from said instruction latch.

12. The processor of claim 1 further comprising means for coupling said top and next registers to store a single, double-precision value and for shifting said double-precision value through said top and next registers.