Coordinated circuit for supplying power from a D-C source to a microcomputer and its semiconductor memories

• US 5,070,481 A
• Filed: 08/05/1986
• Issued: 12/03/1991
• Est. Priority Date: 08/17/1985
• Status: Expired due to Term

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Zobl, Hartmut, Haubner, Georg
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): Ip, Paul
• Application Number:
  US06/893,494
• Time in Patent Office: 1,946 Days
• Field of Search: 307/9 R, 307/110 R, 307/442, 340/52 R, 340/52 F, 340/53, 340/54, 340/55, 340/56, 364/424, 364/431.04, 364/431.11, 364/431.12, 364/422, 364/569, 455/307, 365/226, 365/227, 365/228, 365/229
• US Class Current: 365/228
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A microcomputer (10) in a motor vehicle is supplied with regulated operating voltage through a regulator (12) and a semiconductor (11) for the microcomputer is supplied with voltage from the same vehicle battery, through a voltage divider including a Zener diode, for its chip-select input (CSA) which feeds in through a Schmitt trigger circuit such as to enable writing into the memory (11) when the voltage at that chip-select input lies between upper and lower threshold values. Capacitances connected in parallel to ground where these voltages are respectively connected to the microcomputer and semiconductor memory are so dimensioned that any data statement transfer, begun before the longest delay the microcomputer might have in detecting the voltage drop-off, can be completed in the semiconductor memory before its chip-select input disables any further writing in. In order to keep the stabilizing capacitor (C₄) for the operating voltage supply for the memory down to reasonable size, a separate battery can be advantageous for that voltage supply, although this precaution is less necessary when the memory is a EPROM for recording a one-time message from a crash sensor identifying operating conditions at the beginning of a crash.

Claims

1. A supply voltage network for supplying a microcomputer (10) and at least one memory (11) with energizing voltage derived from a d-c source having a fluctuating output and subject to occasional disconnection from said network, said network also serving for assuring that any data statement, for which a transfer from said microcomputer to said at least one memory has actually begun before recognition by said microcomputer of said disconnection, will be completely written into said at least one memory before said at least one memory becomes disabled, said microcomputer including means for cyclical interrogation of a value representative of voltage received from said d-c source in order to recognize the appearance of said disconnection or of an equivalent battery failure, and said at least one memory having a write-in enabling input for enabling writing into said at least one memory only for a period after application of a voltage exceeding an upper threshold voltage until the applied voltage falls below a lower threshold voltage, said network comprising:

first means, including a first capacitor (C₃) for maintaining an enabling voltage (U₃) at said write-in enabling input (CSA) of said at least one memory which is not less than said lower threshold voltage for a first period (T₄ -T₀) following said disconnection, said first period (T₄ -T₀) being not less than the sum of a minimum interval (Δ

T) required for completing a transfer to said at least one memory of a data statement after initiation of said transfer and a maximum interval (T₃ -T₀) required after said disconnection for said microcomputer to recognize said disconnection by fall-off of voltage (U_B) supplied by said d-c source prior to said disconnection;

second means, including a second capacitor (C₂), for maintaining operating voltage (U₂) of the operation in said microcomputer (10) necessary for said cyclical interrogation and for transfer of data to said at least one memory (11) at a value not less than a predetermined mimimum operating voltage (U_2min) therefore for a second period ending after, or at the same time as, said first period (T₄ -T₀) for which said enabling voltage (U₃) at said write-in enabling input is maintained by said first means at a value not less than said lower threshold voltage, and

third means, including at least a third capacitor (C₄) for maintaining operating voltage (U₄) for said at least one semiconductor memory (11) at a value not less than a predetermined minimum operating voltage therefore for a period ending after, or at the same time as, said first period (T₄ -T₀) for which said enabling voltage is maintained by said first means at a value not less than said lower threshold voltage.

2. Network according to claim 1, wherein a voltage regulator, for said operating voltage (U₂) of at least the operation in said microcomputer necessary for said cyclical interrogation and for transfer of data to said at least one memory is interposed between said second capacitor (C₂) and said d-c source and wherein a fourth capacitor (C₁) is connected across the input of said voltage regulator (12) for prolonging the period after a said disconnection for which said voltage regulator produces a normal regulated output.

3. Network according to claim 1, wherein means including a second voltage source, independent of said d-c voltage source having a fluctuating output voltage, are provided for maintaining operating voltage (U₄) for said at least one memory (11) at a value not less than a predetermined minimum operating voltage therefore for a period ending after, or at the same time as said first period (T₄ -T₀) for which said enabling voltage is maintained by said first means at a value not less than said lower threshold voltage.