Static random access memory

• US 5,070,482 A
• Filed: 04/05/1990
• Issued: 12/03/1991
• Est. Priority Date: 04/06/1989
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Miyaji, Fumio
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/505,157
• Time in Patent Office: 607 Days
• Field of Search: 365/189.01, 365/230.06, 365/154, 365/230.01, 365/190
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

A static RAM in which the threshold voltage of the drive transistors of a memory cell is higher than the threshold voltage of the access transistors, and in which the impedance of the access transistors is lower during writing then during reading, for improving data retention properties of the memory cell. The bit or data lines for reading data from the memory cell is provided with an equalizing circuit and data writing is performed from a writing buffer circuit. This writing buffer circuit is controlled by a pulse generator generating a pulse of a constant predetermined width on the basis of detected address transition to maintain a constant cycle time duration even on the occasion of a continuous write operation.

Claims

1. A semiconductor memory device adapted for data writing and reading, comprising

a plurality of memory cells arranged in a matrix configuration, each memory cell including a pair of access transistors for row selection and a pair of drive transistors cross-coupled to each other to constitute a flipflop circuit, each said access transistor having a threshold voltage lower than the threshold voltage of said drive transistor,

3. The semiconductor memory device according to claim 1 wherein the access transistors and the drive transistors of said memory cells are nMOS transistors,

a resistor load is connected between a junction of said access transistor and said drive transistor and a source voltage line, and wherein

said word line drive means raises the potential of the selected word line to the source voltage during writing and to an intermediate voltage lower than the source voltage and higher than the ground voltage during reading.

2. a plurality of word lines connected to the gates of said access transistors of the memory cells for row selection,

a plurality of bit lines connected to said drive transistors of said memory cells by means of said access transistors to effect data writing or reading, and

word line drive means for driving said word lines so that said access transistors are at a lower impedance during writing than during reading.

4. The semiconductor memory device according to claim 2 wherein said intermediate voltage is lower then the source voltage by the threshold voltage of a MOS transistor.

7. The semiconductor memory device according to claims 4 or 5 wherein said pulse generating means comprises a differentiating circuit for differentiating an address signal transition detection signal.

8. The semiconductor memory device according to claims 4 or 5 wherein said equalizing means precharges said bit or data lines to a predetermined potential.

9. The semiconductor memory device according to claims 4 or 5 wherein said write buffer is connected to said bit or data lines by switching means and adapted to be set to the writing inhibit state by said switching means being turned off.

5. A semiconductor memory device for data writing and reading, comprising

a plurality of memory cells arranged in a matrix configuration for effecting data storage,

a bit line pair which is arranged on both sides of associated memory cells and across which a complementary potential difference apparatus at least during writing,

equalizing means provided across the bit line pair for eliminating the complementary potential difference thereacross during writing, said equalizing means coming into operation before the next write or read cycle,

a write buffer for producing the complementary potential difference across said bit line pair during writing responsive to input data, and

pulse generating means for detecting address transition to generate a pulse of a constant predetermined pulse width to drive said writing buffer by said pulse.

6. A semiconductor memory device for data writing and reading, comprising

a plurality of memory cells arranged in a matrix configuration and responsive to address signals to write or read data into or from each memory cell,

a bit line pair which is provided on both sides of associated memory cells and across which a complementary potential difference appears at least during writing,

a data line pair connected to a plurality of the bit line pairs by means of a column selection switch,

equalizing means provided across the bit line pair and/or the data line pair for eliminating the complementary potential difference across said bit line pair and said data line pair during writing, said equalizing means coming into operation before the next write or read cycle,

a write buffer responsive to input data to produce a complementary potential difference across said bit line pair and said data line pair during writing, and

pulse generating means for detecting the transition of said address signals to generate a pulse of a constant predetermined pulse width to drive said writing buffer by said pulse.