Vertical memory cell array and method of fabrication
First Claim
1. A method of fabricating a vertical memory cell array, using vertical floating gate FET memory cells, in a substrate of a first conductivity type, comprising the steps:
- forming in the substrate multiple rows of doped groundline zones of a second conductivity type extending down to a selected groundline depth;
into each groundline zone, forming a doped channel zone of the first conductivity type extending down to a selected source/channel junction depth, thereby defining a buried source groundline between the source/channel junction and the groundline depth;
into each channel zone, forming a doped drain bitline of the second conductivity type extending down to a selected drain/channel junction depth, thereby defining a buried channel layer between the drain/channel junction and the source/channel junction;
in each bitline row, forming multiple trench areas through said drain bitline, said channel layer and at least partially into said source groundline, thereby defining drain, source and channel regions adjacent each trench, each trench further having substantially vertical sidewalls;
for each trench, forming a gate insulator layer over the substantially vertical sidewalls of said trench;
for each trench, forming a floating gate conductor disposed into the trench, insulated from the associated channel region by the gate insulator;
forming an interlevel insulator layer over said floating gate conductor; and
forming onto the substrate multiple columns of program gate worline conductors extending over respective columns of trenches, insulated from said floating gates by said interlevel insulator.
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Accused Products
Abstract
A vertical memory cell EPROM array (FIGS. 1, 1a and 1b) uses a vertical floating gate memory cell structure that can be fabricated with reduced cell area and channel length. The vertical memory cell memory array includes multiple rows of buried layers that are vertically stacked--a drain bitline (34) over a source groundline (32), defining a channel layer (36) in between. In each bitline row, trenches (22) of a selected configuration are formed, extending through the drain bitline and channel layer, and at least partially into the source groundline, thereby defining corresponding source (23), drain (24) and channel regions (25) adjacent each trench. The array can be made contactless (FIG. 1a), half-contact (FIG. 2a) or full contact (FIG. 2b), trading decreased access time for increased cell area.
228 Citations
11 Claims
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1. A method of fabricating a vertical memory cell array, using vertical floating gate FET memory cells, in a substrate of a first conductivity type, comprising the steps:
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forming in the substrate multiple rows of doped groundline zones of a second conductivity type extending down to a selected groundline depth; into each groundline zone, forming a doped channel zone of the first conductivity type extending down to a selected source/channel junction depth, thereby defining a buried source groundline between the source/channel junction and the groundline depth; into each channel zone, forming a doped drain bitline of the second conductivity type extending down to a selected drain/channel junction depth, thereby defining a buried channel layer between the drain/channel junction and the source/channel junction; in each bitline row, forming multiple trench areas through said drain bitline, said channel layer and at least partially into said source groundline, thereby defining drain, source and channel regions adjacent each trench, each trench further having substantially vertical sidewalls; for each trench, forming a gate insulator layer over the substantially vertical sidewalls of said trench; for each trench, forming a floating gate conductor disposed into the trench, insulated from the associated channel region by the gate insulator; forming an interlevel insulator layer over said floating gate conductor; and forming onto the substrate multiple columns of program gate worline conductors extending over respective columns of trenches, insulated from said floating gates by said interlevel insulator. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of fabricating a vertical memory cell array, using vertical floating gate FET memory cells, in a substrate of a first conductivity type, comprising the steps:
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forming in the substrate multiple rows of doped groundline zones of a second conductivity type extending down to a selected groundline depth; into each groundline zone, forming a doped channel zone of the first conductivity type extending down to a selected source/channel junction depth, thereby defining a buried source groundline between the source/channel junction and the groundline depth; into each channel zone, forming a doped drain bitline of the second conductivity type extending down to a selected drain/channel junction depth, thereby defining a buried channel layer between the drain/channel junction and the source/channel junction; in each bitline row, forming multiple trench areas a through said drain bitline, said channel layer and at least partially into said source groundline, thereby defining drain, source and channel regions adjacent each trench; for each drain bitline, forming a drain contact area at one end of the corresponding row, such that a single electrical contact to all drain regions is made through said drain bitline and said drain contact area; for each source groundline, forming a source contact area at one end of the corresponding row, such that a single electrical contact to all source regions is made through said source groundline and said source contact area; for each trench, forming a gate insulator layer over the walls of such trench; for each trench, forming a floating gate conductor disposed into the trench, insulated from the associated channel region by the gate insulator; forming an interlevel insulator layer over said floating gate conductor; and forming onto the substrate multiple columns of program gate worline conductors extending over respective columns of trenches, insulated from said floating gates by said interlevel insulator. - View Dependent Claims (9)
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10. A method of fabricating a vertical memory cell array, using vertical floating gate FET memory cells, in a substrate of a first conductivity type, comprising the steps:
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forming in the substrate multiple rows of doped groundline zones of a second conductivity type extending down to a selected groundline depth; into each groundline zone, forming a doped channel zone of the first conductivity type extending down to a selected source/channel junction, depth, thereby defining a buried source groundline between the source/channel junction and the groundline depth; into each channel zone, forming a doped drain bitline of the second conductivity type extending down to a selected drain/channel junction depth, thereby defining a buried channel layer between the drain/channel junction and the source/channel junction; in each bitline row, forming multiple trench areas through said drain bitline, said channel layer and at least partially into said source groundline, thereby defining drain, source and channel regions adjacent each trench; for each drain bitline, said bitline being formed wide enough to provide on at least one side of said trenches a drain contact area between bitline rows, such that a separate electrical contact to each drain region is made through such drain contact area; for each trench, forming a gate insulator layer over the walls of such trench; for each trench, forming a floating gate conductor disposed into the trench, insulated from the associated channel region by the gate insulator; forming an interlevel insulator layer over said floating gate conductor; and forming onto the substrate multiple columns of program gate wordline conductors extending over respective columns of trenches, insulated from said floating gates by said interlevel insulator. - View Dependent Claims (11)
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Specification