Semiconductor memory with sequential clocked access codes for test mode entry

• US 5,072,138 A
• Filed: 08/17/1990
• Issued: 12/10/1991
• Est. Priority Date: 08/17/1990
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: McClure, David C., Slemmer, William C., Coker, Thomas A.
• Primary Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US07/570,203
• Time in Patent Office: 480 Days
• Field of Search: 365/95, 365/201, 365/225.7, 365/189.03, 371/21.1, 307/443, 307/449, 307/465, 307/468, 307/469, 377/67
• US Class Current: 326/16
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31719 Security aspects, e.g. preventing unauthorised access during test
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. In addition, sequential codes may be used for further security. Logic for evaluating both a sequence of codes received in parallel from a number of address terminals, and also a sequence of serial codes received at single address terminal, are disclosed. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

Claims

1. An integrated circuit having a normal operating mode, and having a special operating mode enabled by an enable signal, comprising:

a first terminal for receiving a mode initiate signal indicating entry into a special operating mode;

a second terminal for receiving a mode select code;

an evaluation circuit, having inputs coupled to said first and second terminals, and having an output, for presenting a match signal responsive to a mode select code, received at said second terminal in conjunction with said mode initiate signal, matching a preselected value; and

an enable circuit, having an input coupled to the output of said evaluation circuit, and having an output for presenting said enable signal responsive to receipt of a plurality of said match signals.

2. The circuit of claim 1, wherein the preselected values comprise a sequence of different preselected values.

3. The circuit of claim 2, wherein the number of said different preselected values in said sequence is greater than the minimum number required to uniquely select from the available special operating modes.

4. The circuit of claim 1, wherein said enable circuit comprises:

a plurality of latch circuits clocked responsive to receipt of a match signal, wherein the output of a last one of said latch circuits presents said enable signal, and wherein said plurality of latch circuits are connected in series in such a manner that the last one of said latch circuits presents said enable signal responsive to receipt of said plurality of said match signals.

5. The circuit of claim 1, wherein said special operating mode is a special test mode.

6. The circuit of claim 1, wherein said evaluation circuit presents, at its output, first and second match signals responsive to the receipt of mode select codes matching first and second preselected values in first and second sequences, respectively.

7. The circuit of claim 6, wherein said enable circuit comprises:

a first enable circuit, having an input coupled to the output of said evaluation circuit, and having an output for presenting a first enable signal responsive to receipt of a plurality of said first match signals, wherein said first enable circuit is constructed in such a manner that said first enable signal is not presented at its output responsive to receipt of a single first match signal; and

a second enable circuit, having an input coupled to the output of said evaluation circuit, and having an output for presenting a second enable signal responsive to receipt of a plurality of said second match signals, wherein said second enable circuit is constructed in such a manner that said second enable signal is not presented at its output responsive to receipt of a single second match signal.

8. The circuit of claim 7, wherein said first enable circuit comprises:

a plurality of latch circuits clocked responsive to receipt of said first match signals, wherein the output of a last one of said latch circuits presents said first enable signal, and wherein said plurality of latch circuits are connected in series in such a manner that the last one of said latch circuits presents said first enable signal responsive to receipt of a plurality of said first match signals;

and wherein said second enable circuit comprises;

a plurality of latch circuits clocked responsive to receipt of said second match signals, wherein the output of a last one of said latch circuits presents said second enable signal, and wherein said plurality of latch circuits are connected in series in such a manner that the last one of said latch circuits presents said second enable signal responsive to receipt of a plurality of said second match signals.

9. The circuit of claim 8, further comprising:

a functional circuit coupled to said first terminal;

wherein said functional circuit responds to signals having an amplitude in a range between first and second limits when the circuit is in a normal operating mode;

and wherein said mode initiate signal received at said first terminal has an amplitude outside of said range.

10. The circuit of claim 9, further comprising:

an overvoltage detection circuit, coupled between said first terminal and said evaluation circuit, for detecting receipt of said mode initiate signal at said first terminal.

11. The circuit of claim 1, wherein said mode select code is received at a plurality of second terminals.

12. The circuit of claim 11, wherein the number of said plurality of second terminals is -greater than the minimum number required to uniquely select from the available special operating modes.

13. The integrated circuit of claim 12, wherein the circuit does not present a match signal responsive to the value of said code corresponding to the condition where the same logic state is received by all of said plurality of terminals.

14. A method for enabling a special operating mode of a circuit, comprising:

receiving a plurality of mode initiate pulses at a first terminal of said circuit;

receiving a mode select code at a second terminal in conjunction with receipt of each of said mode initiate pulses, said mode select codes indicative of a special operating mode to be enabled; and

generating a special mode enable signal responsive to said plurality of received mode select codes matching preselected values;

wherein said special mode enable signal is not generated responsive to receipt of the first of said plurality of mode initiate pulses.

15. The method of claim 14 further comprising:

storing an indication of the number of matches between said mode select codes and the preselected values;

and further comprising;

resetting said indication, responsive to the evaluating of a mode select code which does not match its preselected value.

16. The method of claim 14, wherein said preselected values do not match one another.

17. The method of claim 14, wherein the step of generating the special mode enable signal comprises:

clocking a first series of latches responsive to receipt of values of said mode select codes matching a first sequence of preselected values; and

clocking a second series of latches responsive to receipt of values of said mode select codes matching a second sequence of preselected values;

wherein the latches in each of said first and second series of latches are connected in series in such a manner that the last ones of said first and second series of latches presents first and second special mode enable signals, respectively, at their respective outputs.

18. The method of claim 14, wherein said generating step comprises:

evaluating each of said plurality of received mode select codes responsive to each of said mode initiate pulses received at said first terminal.

19. The method of claim 18, wherein said preselected values comprise a sequence of different mode select code values.

20. The circuit of claim 19, wherein the number of said different mode select code values in said sequence is greater than the minimum number required to uniquely select from the available special operating modes.

21. A circuit for enabling a special operating mode, comprising:

a first terminal for receiving a mode initiate signal;

a second terminal for receiving mode select codes;

a plurality of latches connected in series with one another, a first one of said plurality of latches having a known logic state connected to its data input, and a last one of said plurality of latches generating an enable output at its output;

an evaluation circuit for presenting a clock signal to a first of said plurality of latches responsive to a first mode select code, received in conjunction with a mode initiate signal, matching a first predetermined value, and wherein said evaluation circuit presents a clock signal to a second of said plurality of latches responsive to a second mode select code, received in conjunction with another mode initiate signal, matching a second predetermined value.

22. The circuit of claim 21, further comprising:

a second plurality of latches connected in series with one another, a first one of said second plurality of latches having a known logic state connected to its data input, and a last one of said second plurality of latches generating an enable output at its output;

and wherein said evaluation circuit is for presenting a clock signal to a first of said second plurality of latches responsive to a first mode select code, received in conjunction with a mode initiate signal, matching a third predetermined value, and wherein said evaluation circuit presents a clock signal to a second of said second plurality of latches responsive to a second mode select code, received in conjunction with a mode initiate signal, matching a fourth predetermined value.

23. The circuit of claim 21, wherein said mode select codes are received at a plurality of said second terminals in conjunction with a mode initiate signal.

24. The circuit of claim 23, wherein the number of said plurality of second terminals exceeds the minimum number required to uniquely select the available special operating modes.

25. The circuit of claim 23, wherein none of said predetermined values of mode select codes is represented by a digital value having all bits at the same state.

26. The circuit of claim 21, wherein said evaluation logic comprises:

a storage circuit for storing a sequence of said mode select codes received at said second terminal in conjunction with a plurality of said mode initiate signals;

a clocking circuit for presenting a first clock signal to said plurality of latches responsive to the contents of said storage circuit matching said first predetermined value.

27. The circuit of claim 26, wherein said clocking circuit also is for presenting a second clock signal to said plurality of latches responsive to the contents of said storage circuit matching said second predetermined value.

28. The circuit of claim 27, wherein said first and second predetermined values are the same.

29. The circuit of claim 27, wherein said storage circuit comprises a shift register.

30. The circuit of claim 29, wherein said clocking circuit comprises:

logic circuitry having inputs connected to outputs of said shift register, for presenting a match signal responsive to the outputs of said shift register matching said second predetermined value;

a counter for counting the number of mode initiate pulses received and for presenting a compare signal responsive to the number of mode initiate pulses received reaching a predetermined count; and

a clocking gate, for presenting said second clock signal to said plurality of latches responsive to said match signal and said compare signal.

31. The circuit of claim 30, wherein said clocking gate is also responsive to the state of said plurality of latches, in such a manner that said second clock signal is not presented responsive to said latches indicating that a first clock signal has been generated matching a value other than said first predetermined value.