Method and apparatus for testing logic circuitry by applying a logical test pattern

• US 5,072,178 A
• Filed: 06/04/1990
• Issued: 12/10/1991
• Est. Priority Date: 06/09/1989
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Matsumoto, Takashi
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): Nguyen, Vinh P.
• Application Number:
  US07/532,447
• Time in Patent Office: 554 Days
• Field of Search: 324/73.1, 324/158 R, 371/27, 371/15.1, 371/22.3, 371/22.6, 371/16.1, 371/25.1
• US Class Current: 714/724
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G06F 2201/865 Monitoring of software

Abstract

A testing method of a logic circuit which can change test data in a testing apparatus and an apparatus which is used for the testing method are disclosed. The logic circuit testing apparatus having a first storage to store test data including a plurality of test patterns and a second storage to store each of the test patterns in correspondence to a group of tester pins further has a transfer circuit including a data converter to change the test patterns from the first storage and a third storage to store control data to control the data converter. The transfer circuit transfers each of the test patterns from the first storage to the second storage. When the test pattern is transferred by the transfer circuit, the test pattern is changed by the data converter by the control data.

Claims

1. A logic circuit testing apparatus comprising:

a first storage means for storing test data including a plurality of logical test patterns;

a second storage means for storing each of the logical test patterns in correspondence to a group of tester pins;

a third storage means for storing control data to control a data convert means;

a data convert means for converting data from said first storage means on the basis of the control data stored in said third storage means;

a test means for testing a logic circuit which applies the logical test patterns from said second storage means to the logic circuit; and

control means for selectively controlling each of the first, second, and the third storage means, the data convert means, and the test means,

said control means transferring the test data from the first storage means, via the data convert means which logically converts the data on the basis of the control data from the third storage means or directly, to the second storage means to be stored as a logical test pattern,

said control means transferring logical test pattern stored in the second storage means to the test means to test the logic circuit.

2. An apparatus according to claim 1, wherein each of the logical test patterns in the first storage means is accompanied with information to designate a pin number assigned to each bit of each logical test pattern, each of the storing positions in the third storage means has an address corresponding to the pin number, and a reading position of the control data is designed by the pin number discrimination information which was read out of the first storage means together with the logical test pattern.

3. A logic circuit testing apparatus comprising:

a first storage means for storing logic circuit test data including a plurality of logical test patterns;

a second storage means for storing each of the logical test patterns in correspondence to a group of tester pins;

a third storage means for storing control data to control a data convert means;

a data convert means for converting data from said first storage means on the basis of the control data stored in said third storage means;

wherein said data convert means includes a logic circuit to selectively execute a plurality of kinds of logic operations between the logical test patterns from the first storage means and data representative of change of the test data stored in the third storage means, and said control data includes said data representative of a change of the test data and operation designation information to designate arbitrary one of said plurality of kinds of logic operations, a test means for testing a logic circuit which applies the logical test patterns from said second storage means to the logic circuit.

4. An apparatus according to claim 3, wherein each of the logical test patterns in the first storage means is accompanied with information to designate a pin number assigned to each bit of each logical test pattern, each of the storing positions in the third storage means has an address corresponding to the pin number, and a reading position of the control data is designated by the pin number discrimination information which was read out of the first means storage together with the logical test pattern.

5. An apparatus according to claim 3, wherein the logical test pattern held in the first storage means is replaced to the changing data by the data convert means by the designation of the operation designation information.

6. An apparatus according to claim 3, wherein the logical test pattern held in the first storage means is inverted by the designation of the operation designation information.

7. An apparatus according to claim 3, wherein the logical test pattern held in the first storage means is outputted from the logic circuit by the designation of the operation designation information.

8. An apparatus according to claim 3, wherein the logic circuit includes a discriminating circuit to discriminate whether the logical test pattern satisfies the condition designated by the operation designation information or not.

9. An apparatus according to claim 8, wherein in the case where it is determined by the discriminating circuit that the logical test pattern satisfies the condition designated by the operation designation information, the logic circuit executes the logic operation between the logical test pattern and at least the data for change of the test data.

10. An apparatus according to claim 8, wherein in the case where it is determined by the discriminating circuit that the logical test pattern does not satisfy the condition designated by the operation designation information, the logic circuit outputs the logical test pattern.

11. A method for testing a logic circuit comprising the steps of:

holding test data including a plurality of logical test patterns in a first storage;

holding control data in a third storage;

changing logically the logical test patterns from the first storage on the basis of control data from a third storage to transfer to a second storage;

holding the transferred logical test patterns into the second storage in correspondence to a group of test pins; and

applying the logical test pattern held in the second storage to said logic circuit.

12. A method according to claim 11, wherein said data changing step includes the steps of:

designating arbitrary one of a plurality of kinds of logic operations by operation designation information; and

executing the logic operation on the basis of the operation designation information.

13. A method according to claim 12, wherein in the step of executing the logic operation, further, a check is made to see if the logical test pattern satisfies the condition designated by the operation designation information or not and the logic operation is executed on the basis of the result of such a discrimination.