Phase-locked loop with clamped voltage-controlled oscillator

• US 5,072,195 A
• Filed: 04/05/1990
• Issued: 12/10/1991
• Est. Priority Date: 04/05/1990
• Status: Expired due to Fees

• Current Assignee: Gazelle Microcircuits, Inc.
• Original Assignee: Gazelle Microcircuits, Inc.
• Inventors: Chen, Wei, Graham, Andrew C., Fitzpatrick, Mark E.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US07/505,851
• Time in Patent Office: 614 Days
• Field of Search: 331/2, 331/11, 331/25, 331/27, 331/1 A
• US Class Current: 331/2
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range

Abstract

A phase-locked loop responsive to both phase and frequency difference between the incoming signal and the feedback signal is provided. Using a reference signal, this phase-locked loop accepts a wide range of frequencies similar to a phase-locked loop having a phase frequency detector, and also achieves the noise performance of a phase-locked loop having only a simple phase detector. In one embodiment, the phase-locked loop is a combination including first and second phase-locked loops. The reference signal is provided to the first phase-locked loop, which includes a phase frequency detector. This first phase-locked loop is used to control a second phase-locked loop, which includes a phase detector. A voltage clamp can also be provided to enhance the ability to lock a signal among several signals, or from a noisy background.

Claims

1. A circuit receiving an input signal and generating an output signal, comprising:

first and second voltage controlled oscillators, said first voltage controlled oscillator providing a control signal, said second voltage controlled oscillator operatively coupled to said input signal and providing said output signal; and

constraining means receiving said control signal for limiting the voltage swing at an input terminal of said second voltage controlled oscillator to thereby constrain the frequency range of operation of said second voltage controlled oscillator in accordance with said control signal, wherein said constraining means comprises a clamping circuit.

2. A circuit as in claim 1, wherein said first voltage controlled oscillator receives a reference signal, said reference signal determining a value of said control signal.

3. A circuit receiving an input signal and generating an output signal, comprising:

first and second phase-locked loops said first phase-locked loop providing a control signal, said second phase-locked loop receiving said input signal and providing said output signal; and

constraining means receiving said control signal for limiting the voltage swing at an input terminal of said second phase-locked loop to thereby constrain the frequency range of operation of said second phase-locked loop in accordance with said control signal, wherein said constraining means comprises a clamping circuit.

4. A circuit as in claim 3, wherein said first phase-locked loop receives a reference signal, said reference signal determining a value of said control signal.

5. An apparatus receiving first and second input signals, said apparatus comprising:

(a) a first phase-locked loop receiving said first input signal and providing a center frequency based on said first input signal comprising;

(i) first voltage-controlled oscillator for receiving a phase and frequency correction signal, and for providing a first feedback signal responsive to said phase and frequency correction signal; and

(ii) phase frequency detector and filter means for detecting a phase and frequency difference between said first input signal and said first feedback signal, and for providing said phase and frequency correction signal responsive to said phase and frequency difference;

(b) a second phase-locked loop receiving said second input signal comprising;

(i) second voltage-controlled oscillator, substantially the same as said first voltage-controlled oscillator, for receiving a correction signal, and for providing a second feedback signal responsive to said correction signal; and

(ii) phase detector and filter means for detecting a phase difference between said second input signal and said second feedback signal, and for providing a phase correction signal responsive to said phase difference;

(c) constraining means constraining the frequency range of said second phase-locked loop such that said second phase-locked loop locks on said second input signal if said second input signal is within a pull-in range centered around said center frequency, comprising;

(i) summation means for receiving said phase and frequency correction signal and said phase correction signal and for providing a summed signal to said second voltage controlled oscillator; and

(ii) a voltage clamp connecting said phase and frequency detector and filter means, such that the difference between said phase and frequency correction signal and said phase correction signal is constrained to within a predetermined voltage interval.

6. An apparatus as in claim 5, wherein said phase frequency detector and filter means comprises:

a phase frequency detector responsive to both phase difference and frequency difference between said first input signal and said first feedback signal, said phase frequency detector providing a phase and frequency difference signal; and

a first filter means for receiving said phase and frequency difference signal and providing said phase and frequency correction signal.

7. An apparatus as in claim 6, wherein said phase detector and filter means comprises:

a phase detector means responsive to phase difference between said second input signal and said second feedback signal, said phase detector providing a phase difference signal; and

a second filter means for receiving said phase difference signal and providing said phase correction signal.

8. An apparatus as in claim 7, wherein said first filter and second filter means each comprises:

a first capacitor having first and second terminals;

a resistor having first and second terminals, said first terminal of said resistor connected to said second terminal of said first capacitor forming a common terminal; and

a second capacitor also having first and second terminals, said first terminal of said second capacitor connected to said first terminal of said first capacitor, and said second terminal of said second capacitor connected to said second terminal of said resistor.

9. An apparatus as in claim 8, wherein said voltage clamp connects said common terminal of said first filter means and said common terminal of said second filter means.

10. An apparatus as in claim 5, wherein said summation means comprises:

a first resistor having first and second terminals, said first terminal receiving said phase and frequency correction signal; and

a second resistor also having first and second terminals, said first terminal of said second resistor receiving said phase correction signal, said second terminal of said second resistor connected to said second terminal of said first resistor, and said second terminal of said second resistor providing said correction signal of said second voltage-controlled oscillator.

11. An apparatus as in claim 5, wherein said voltage clamp comprises:

a reference terminal;

a clamped terminal;

first voltage limiting means for preventing voltage at said clamped terminal to be smaller than voltage at said reference terminal by more than a first predetermined voltage; and

second voltage limiting means for preventing said voltage at said clamped terminal to be greater than voltage at said reference terminal by more than a second predetermined voltage.

12. An apparatus as in claim 11, wherein said first voltage limiting means comprises:

a reference transistor having control, first and second terminals;

a clamp transistor, also having control, first and second terminals, said second terminal of said clamp transistor connected to said second terminal of said reference transistor to form a differential pair, and said control terminal of said clamp transistor receiving a signal responsive to the voltage at said clamped terminal;

preset voltage means having first and second terminals for providing said first predetermined voltage across its first and second terminals, said first terminal of said preset voltage means connected to said reference terminal and said second terminal of said preset voltage means connected to said control terminal of said reference transistor; and

current drive means for driving current into said clamped terminal when the voltage at said control terminal of said reference transistor is greater than the voltage at said control terminal of said clamped transistor;

13. An apparatus as in claim 12, further comprising:

a first current source connected to said second terminal of said clamp transistor for providing a first substantially constant current; and

second current source connected to said first terminal of said clamp transistor for providing a second substantially constant current, said second substantially constant current being less than said first substantially constant current.

14. An apparatus as in claim 13, wherein said first current source comprises a depletion mode transistor and a resistive element.

15. An apparatus as in claim 13, wherein said second current source comprises a depletion mode transistor and a resistive element.

16. An apparatus as in claim 12, wherein said preset voltage means comprises a resistor.

17. An apparatus as in claim 12, wherein said current drive means comprises a diode.

18. An apparatus as in claim 11, wherein said second voltage limiting means comprises:

a reference transistor having control, first and second terminals, said control terminal of said reference transistor receives a signal responsive to the voltage at said reference terminal;

a clamp transistor, also having control, first and second terminals, said second terminal of said clamp transistor connected to said second terminal of said reference transistor to form a differential pair;

preset voltage means having first and second terminals for providing said first predetermined voltage across its first and second terminals, said first terminal of said preset voltage means connected to said clamped terminal and said second terminal of said preset voltage means connected to said control terminal of said clamp transistor; and

current drive means for sinking current from said clamped terminal when the voltage at said control terminal of said reference transistor is smaller than the voltage at said control terminal of said clamped transistor.

19. An apparatus as in claim 18, further comprising:

first current source connected to said second terminal of said clamp transistor for providing a first substantially constant current; and

second current source connected to said first terminal of said clamp transistor for providing a second substantially constant current, said second substantially constant current being less than one half of said first substantially constant current.

20. An apparatus as in claim 19, wherein said first current source comprises a depletion mode transistor and a resistive element.

21. An apparatus as in claim 19, wherein said second current source comprises a depletion mode transistor and a resistive element.

22. An apparatus as in claim 18, wherein said preset voltage means comprises a resistor.

23. An apparatus as in claim 18, wherein said current drive means comprises a transistor.

24. An apparatus as in claim 18, further comprising a clamping diode having a cathode and an anode, said anode of said clamping diode connected to said first terminal of said clamp transistor, and said cathode of said clamping diode connected to said second terminal of said clamp transistor.

25. An apparatus as in claim 18, wherein said current drive means comprises a diode.