Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry

• US 5,072,266 A
• Filed: 12/27/1988
• Issued: 12/10/1991
• Est. Priority Date: 12/27/1988
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Bulucea, Constantin, Rossen, Rebecca
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Kim, Daniel Y. J.
• Application Number:
  US07/290,546
• Time in Patent Office: 1,078 Days
• Field of Search: 357/23.4, 357/23.8, 357/23.1, 437/38
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned in order to suppress oxide dielectric breakdown, using a shaped deep body junction that partly lies below the trench bottom to force voltage breakdown away from the trench surfaces and into the bulk of the semiconductor material, and using special procedures for growth of gate oxide at various trench corners.

Claims

1. A trench DMOS transistor cell comprising:

a substrate of semiconductor material of heavily doped first electrical conductivity type;

a first covering layer of semiconductor material of said first electrical conductivity type lying on the substrate;

a second covering layer of semiconductor material of second electrical conductivity type lying on the first covering layer;

a third covering layer of semiconductor material of heavily doped said first electrical conductivity type and having a top surface and partly lying over the second covering layer, wherein a portion of the second covering layer is heavily doped and this portion extends both vertically upward and downward, an upward portion extending through the third covering layer to the top surface of the third covering layer and a downward portion extending downward into the first covering layer;

a trench having a bottom surface and side surfaces and extending vertically downward from the top surface of the third covering layer through the third covering layer and the second covering layer and through a portion of the first covering layer, wherein the bottom surface of the trench lies above a lowest part of the downward portion of the second covering layer;

electrically conducting semiconductor material positioned within the trench;

a layer of oxide positioned within the trench between the electrically conducting semiconductor material and the bottom and side surfaces of the trench; and

three electrodes electrically coupled to the electrically conducting semiconductor material, to the third covering layer and to the substrate, respectively.

2. A trench DMOS transistor cell comprising:

a substrate of semiconductor material of heavily doped first electrical conductivity type having a top surface;

a first covering layer of semiconductor material of first electrical conductivity type having a top surface and being contiguous to and overlying the substrate top surface;

a second covering layer of semiconductor material of second electrical conductivity type having a top surface and being contiguous to the top surface of the first covering layer and extending vertically downward from the top surface of the first covering layer into an upper portion of the first covering layer;

a third covering layer of semiconductor material of heavily doped first electrical conductivity type having a top surface and being contiguous to and partly overlying the top surface of the second covering layer, wherein a portion of the second covering layer is heavily doped and this portion extends vertically upward through the third covering layer to the top surface of the third covering layer and forms an exposed pattern of the second covering layer adjacent in the top surface of the third covering layer, wherein the maximum depth of the heavily doped portion of the second covering layer relative to the top surface of the third covering layer is a predetermined number d₁, and wherein the depth of the top surface of the substrate at a position that underlies the position of maximum depth of the heavily doped portion of the second covering layer is a second predetermined number d₂ ;

a trench having side surfaces and bottom surfaces and extending vertically downward from the top surface of the third covering layer through the third covering layer, through the second covering layer and through a portion of, but not all of, the first covering layer, the trench bottom surface having a maximum depth relative to the top surface of the third covering layer equal to a third predetermined number d₃ where d₃ <

d₁, wherein the trench in horizontal cross section is approximately a polygonal stripe with stripe width approximately equal to a fourth predetermined number b, and wherein this polygonal stripe laterally surrounds and is spaced apart from the exposed pattern of the second covering layer at the top surface of the third covering layer;

a layer of oxide, positioned within the trench and contiguous to the bottom surfaces and side surfaces of the trench so that a portion of, but not all of, the trench is filled with this oxide layer;

electrically conducting semiconductor material, having resistivity of approximately one ohm-cm, that is contiguous to the oxide layer and positioned within the trench so that this electrically conducting semiconductor material is spaced apart from the side walls and the bottom walls of the trench by the oxide layer; and

three electrodes that are electrically coupled to the electrically conducting semiconductor material in the trench, to the third covering layer and to the substrate, respectively.

3. A cell according to claim 2, wherein said substrate has a doping concentration of at least 10¹⁸ cm^-3.

4. A cell according to claim 2, wherein said first covering layer has a doping concentration in the range of 10¹⁵ -10¹⁷ cm^-3.

5. A cell according to claim 2, wherein said vertically extending portion of said second covering layer has a doping concentration of at least 10¹⁸ cm^-3.

6. A cell according to claim 2, wherein said third covering layer has a doping concentration at the top surface of at least 5×

10¹⁹ cm^-3.

7. A cell according to claim 2, wherein the shape of said polygonal stripe is drawn from the class consisting of

8. A cell according to claim 2, wherein said second covering layer exposed pattern has the shape of a hexagon.

9. A cell according to claim 2, further comprising a second oxide layer contiguous to said electrically conducting semiconductor material within said trench.

10. A cell according to claim 9, further comprising a trench-filling semiconductor material that is contiguous to said second oxide layer within said trench and that substantially fills the remainder of said trench.

11. A cell according to claim 2, wherein the difference d₁ -d₃ between said predetermined numbers d₁ and d₃ is 0.5 μ

m or greater.

12. A cell according to claim 2, wherein the difference d₂ -d₃ between said predetermined numbers d₁ and d₃ is 0.5 μ

m or greater.

13. A cell according to claim 2, wherein said trench oxide layer has a thickness on said side surfaces and said bottom surfaces of said trench that lies in the range 0.1-0.2 μ

m.

14. The trench DMOS transistor cell according to claim 2, wherein said heavily doped portion of said second covering layer is centrally located within said polygonal stripe whereby that said heavily doped portion forces semiconductor avalanche breakdown to occur away from said trench.