Dynamic ram and method of manufacturing the same

• US 5,072,269 A
• Filed: 03/15/1989
• Issued: 12/10/1991
• Est. Priority Date: 03/15/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hieda, Katsuhiko
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US07/323,752
• Time in Patent Office: 1,000 Days
• Field of Search: 357/23.4, 357/23.6, 357/45, 357/51, 357/55
• US Class Current: 257/302
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical
• CPC Class Codes: Y10S 257/911 Light sensitive array adapted to be scanned by electron beam, e.g. vidicon device

Abstract

A semiconductor memory device includes a plurality of semiconductor pillar projections separated by grooves formed in longitudinal and transverse directions in a substrate and arranged in a matrix manner, a MOS capacitor and a MOSFET formed on side surfaces at lower and upper portions, respectively, of each pillar projection, a diffusion layer of a source or drain of each MOSFET formed in an upper end face of the pillar projection, and a bit line connected to the diffusion layer. The bit line is in contact with the upper end face of the pillar projection in a self-alignment manner.

Claims

1. A dynamic RAM comprising:

a semiconductor substrate;

a plurality of semiconductor pillar projections separated by grooves formed in longitudinal and transverse directions in said semiconductor substrate, said semiconductor pillar projections being arranged in a matrix manner;

a plurality of MOS capacitors formed on side surfaces at a lower portion of each of said semiconductor pillar projections, said each MOS capacitor including

a memory node formed in the side surfaces at the lower portion of each semiconductor pillar projection,

a capacitor insulating film formed on the side surfaces at the lower portion of each semiconductor pillar projection, covering said memory node, and

a capacitor electrode formed on said capacitor insulating film;

a plurality of MOSFETS formed on side surfaces at an upper portion of each semiconductor pillar projection, said each MOSFET including

a channel region formed at least on the side surfaces at the upper portion of each semiconductor pillar projection,

source and drain regions formed above and below said channel region to sandwich said channel region,

a gate insulating film formed on the side surfaces at the upper portion of each semiconductor pillar projection in which said channel region is formed, and

a gate electrode formed over said channel region and only on a portion of said gate insulating film formed on the side surfaces at the upper portion of each semiconductor pillar projection; and

a bit line connected to an upper surface of each semiconductor pillar projections, said bit line being in contact with an upper end face of each semiconductor pillar projection.

2. A dynamic RAM according to claim 1, wherein said semiconductor pillar projections have upper and lower portions which define a step therebetween.

3. The dynamic RAM according to claim 2, wherein said memory node includes a diffusion layer formed on the side surfaces at the lower portion of each semiconductor pillar projection, said diffusion layer being deep enough to reach at least the side surfaces at the upper portion of each semiconductor pillar projection.

4. A dynamic RAM comprising:

a semiconductor substrate;

an insulating layer buried in said semiconductor substrate;

a plurality of semiconductor pillar projections separated by grooves formed in longitudinal and transverse directions in said semiconductor substrate, said semiconductor pillar projections being arranged in a matrix manner and formed on said insulating layer;

a plurality of MOS capacitors formed on side surfaces at a lower portion of each of said semiconductor pillar projections, said each MOS capacitor including

a memory node formed in the side surfaces at the lower portion of each semiconductor pillar projection,

a capacitor insulating film formed on the side surfaces at the lower portion of each semiconductor pillar projection, covering said memory node, and

a capacitor electrode formed on said capacitor insulating film;

a plurality of MOSFETS formed on side surfaces at an upper portion of each semiconductor pillar projection, said each MOSFET including

a channel region formed at least on the side surfaces at the upper portion of each semiconductor pillar projection,

source and drain regions formed above and below said channel region to sandwich said channel region,

a gate insulating film formed on the side surfaces at the upper portion of each semiconductor pillar projection in which said channel region is formed, and

a gate electrode formed over said channel region and only on a portion of said gate insulating film formed on the side surfaces at the upper portion of each semiconductor pillar projection; and

a bit line connected to an upper surface of each semiconductor pillar projections.

5. The dynamic RAM according to claim 4, wherein a memory cell is formed in each of said semiconductor pillar projections.

6. The dynamic RAM according to claim 4 wherein said buried insulating layer is formed by bonding semiconductor substrates having insulating films thereon.

7. The dynamic RAM according to claim 4, wherein said bit line is in contact with each of said semiconductor pillar projections in a self-alignment manner.

8. A dynamic RAM comprising:

a semiconductor substrate;

an insulating layer buried in said semiconductor substrate;

a plurality of semiconductor pillar projections separated by grooves formed in longitudinal and transverse directions in said semiconductor substrate, said semiconductor pillar projections being arranged in a matrix manner and having upper and lower portions which define a step therebetween on side surfaces of said semiconductor pillar projection such that said semiconductor pillar projection is narrower at said upper portion than said lower portion;

a plurality of MOS capacitors formed on side surfaces at the lower portion of each of said semiconductor pillar projections, said each MOS capacitor including

a memory node formed in the side surfaces at the lower portion of each semiconductor pillar projection,

a capacitor insulating film formed on the side surfaces at the lower portion of each semiconductor pillar projection, covering said memory node, and

a capacitor electrode formed on said capacitor insulating film;

a plurality of MOSFETs formed on the side surfaces at the upper portion of each semiconductor pillar projection, said each MOSFET including

a channel region formed at least on the side surfaces at the upper portion of each semiconductor pillar projection,

source and drain regions formed above and below said channel region to sandwich said channel region,

a gate insulating film formed on the side surfaces at the upper portion of each semiconductor pillar projection in which said channel region is formed, and

a gate electrode formed over said channel region and only on a portion of said gate insulating film formed on the side surfaces at the upper portion of each semiconductor pillar projection; and

a bit line connected to an upper surface of each semiconductor pillar projections.

9. The dynamic RAM according to claim 8, wherein said memory node includes a diffusion layer formed in the side surface at the lower portion of each semiconductor pillar projection, said diffusion layer being deep enough to reach at least the side surface at the upper portion of each semiconductor pillar projection.

10. A dynamic RAM comprising:

a semiconductor substrate;

a plurality of semiconductor pillar projections separated by grooves formed in longitudinal and transverse directions in said semiconductor substrate, said semiconductor pillar projections being arranged in a matrix manner;

said matrix being divided into a plurality of blocks each containing a predetermined number of said semiconductor pillar projections;

a plurality of MOS capacitors formed on side surfaces at a lower portion of each of said semiconductor pillar projections, said each MOS capacitor including

a memory node formed in the side surfaces at the lower portion of each semiconductor pillar projection,

a capacitor insulating film formed on the side surfaces at the lower portion of each semiconductor pillar projection, covering said memory node, and

a capacitor electrode formed on said capacitor insulating film;

a plurality of MOSFETS formed on side surfaces at an upper portion of each semiconductor pillar projection, said each MOSFET including

a channel region formed at least on the side surfaces at the upper portion of each semiconductor pillar projection,

source and drain regions formed above and below said channel region to sandwich said channel region,

a gate insulating film formed on the side surfaces at the upper portion of each semiconductor pillar projection in which said channel region is formed, and

a gate electrode formed over said channel region and only on a portion of said gate insulating film formed on the side surfaces at the upper portion of each semiconductor pillar projection;

a bit line connected to an upper surface of each semiconductor pillar projections; and

at least one contact semiconductor pillar projection formed in each of said blocks and comprising a first insulating layer which is thicker than said gate insulating film of said MOSFET and is formed on an upper surface of said contact semiconductor pillar projection, and a word line contact pad formed on said first insulating layer, said contact pad being electrically connected to said gate electrodes of memory cells in each block.

11. The dynamic RAM according to claim 10, wherein said contact pillar projection is arranged close to a center of each block.

12. The dynamic RAM according to claim 10, wherein said semiconductor pillar projection is formed on a second insulating layer buried in said semiconductor substrate.

13. The dynamic RAM according to claim 12, wherein said buried second insulating layer is formed by bonding semiconductor substrates each having an insulating film thereon.