Semiconductor memory device having memory cells including IG FETs in a symmetrical arrangement

• US 5,072,286 A
• Filed: 09/25/1990
• Issued: 12/10/1991
• Est. Priority Date: 09/28/1989
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamanaka, Toshiaki, Minami, Masataka, Shukuri, Shoji, Hirao, Mitsuru
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US07/587,974
• Time in Patent Office: 441 Days
• Field of Search: 357/42, 357/45, 357/59 G, 365/156
• US Class Current: 257/208
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A semiconductor memory device has memory cells each including first and second inverters cross-coupled to each other through first and second interconnecting conductors for forming a bistable circuit and first and second transfer gates connected between the first inverter and address signal conductors and between the second inverter and the address signal conductors, respectively. The first and second interconnecting conductors are arranged substantially point-symmetrically and have at least portions substantially parallel with each other on a surface of a substrate, and IG FETs constituting the first and second inverters have their gate electrodes arranged substantially parallel with one another and extending in a direction substantially perpendicular to the parallel portions of the first and second interconnecting conductors for the cross-coupling on the surface of the substrate.

Claims

1. A semiconductor memory device including a plurality of semiconductor memory cells formed in a surface of a semiconductor substrate and arranged in rows and columns, each of said memory cells being connected with first and second address signal conductors for writing/reading information in the memory cell, said each memory cell comprising:

first and second insulated gate field effect transistor (IG FET) inverters cross-coupled to each other through first and second interconnecting conductors to constitute a bistable circuit;

a first IG FET transfer gate connected between said address signal conductors and said first inverter, said first IG FET transfer gate being connected with said first inverter through said second interconnecting conductor; and

a second IG FET transfer gate connected between said address signal conductors and said second inverter, said second IG FET transfer gate being connected with said second inverter through said first interconnecting conductor, in which

said first and second interconnecting conductors are arranged substantially point-symmetrically and have at least portions substantially parallel with each other on said surface of said substrate, and

IG FETs constituting said first and second inverters have their gate electrodes arranged substantially parallel with one another and extending in a direction substantially perpendicular to said parallel portions of said first and second interconnecting conductors for said cross-coupling on said surface of said substrate, and IG FETs constituting said first and second transfer gates have their gate electrodes arranged substantially parallel with those of said IG FETs constituting said first and second inverters and forming part of one of said address signal conductors on said surface of said substrate.

2. A semiconductor memory device according to claim 1, in which said first and second interconnecting conductors generally extend substantially rectilinearly.

3. A semiconductor memory device according to claim 2, in which said IG FETs constituting said first and second inverters and said first and second transfer gates have their source/drain regions and gate electrodes arranged substantially point-symmetrically.

4. A semiconductor memory device according to claim 1, in which IG FETs constituting said first and second inverters and said first and second transfer gates have their source/drain regions and gate electrodes arranged substantially point-symmetrically.

5. A semiconductor memory device according to claim 1, in which said first and second interconnecting conductors are substantially U-shaped and interdigitated with each other.

6. A semiconductor memory device according to claim 5, in which said IG FETs constituting said first and second inverters and said first and second transfer gates have their source/drain regions and gate electrodes arranged substantially line-symmetrically.

7. A semiconductor memory device including a plurality of memory cells formed in a suface of a semiconductor substrate, each memory cel comprising a first inverter circuit including a series connection of a fist load IG FET (insulated gate FET) of a first conductivity type with a first driver IG FET of a second conductivity type, a second inverter circuit including a series connection of a second load IG FET of said first conductivity type with a second driver IG FET of said second conductivity type, and fist and second transfer IG FETs of said second conductivity type for controlling said fist and second inverter circuits, respectively, said first and second load IG FETs having their source/drain regions and gate electrodes arranged substantially symmetrically;

said fist driver FET having its source/drain regions and gate electrodes arranged substantially symmetric with those of said second driver FET, and said fist transfer IG FET having their source/drian regions a nd gate electrodes arranged substantial symmetrically with those of said second transfer FET,

wherein the gate electrodes of said six IG FETs ae arranged substantially parallel with each other.

8. A semiconductor memory device according to claim 7, further including:

a first interconnecting conductor formed over a suface of said semiconductor substrate for connecting a gate electrode of said first load IG FET of said first conductivity type, a gate electrode of the first driver IG FET of said second conductivity type, a source/drain region of the second load IG FET of said first conductivity type, a source/drain region of the second driver IG FET of said second conductivity type, and a source/drain region of the second transfer IG FET of said second conductivity type, with each other; and

a second interconnecting conductor formed over the surface of said semiconductor substrate of connecting a gate electrode of said second load IG FET of said first conductivity type, a gate electrode of said second driver IG FET of said second conductivity type, a source/drain region of said first load IG FET of one conductivity type, a source/drain region of said first die IG FET f said second conductivity type, and a source/drain region of said first transfer IG FET of said first conductivity type, with each other.

9. A semiconductor memory device according to claim 8, win which said first and second interconnecting conductors are substantially rectilinear and are arranged in a substantially parallel relationship with each other.

10. A semiconductor memory device according to claim 7 in which said first and second load IG FETs have their source/drain regions and gate electrodes arranged in a substantially point-symmetrical relationship with respect to one point, said first driver IG FET has its source/drain regions and its gate electrode arranged substantially point-symmetrical with those of said second driver IG FET with respect to said point and arranged so as to be across said two load IG FETs from the latter, said first transfer IG FET has its source/drain regions and its gate electrode arranged substantially point-symmetrical with those of said second transfer IG FET with respect to said point and arranged so as to be across said two load IG FETs from the latter.

11. A semiconductor memory device according to claim 10, in which said first transfer IG FET has its source/drain regions and its gate electrode arranged substantially point-symmetrical with those of said second transfer IG FET with respect to said point and arranged so as to be across said two load IG FETs and said two driver IG FETs from the latter.

12. A semiconductor memory device according to claim 7, in which lead electrodes for source/drain regions of said IG FETs are formed by a self-alignment using field insulating layers as a mask.

13. A semiconductor memory device according to claim 7, in which each memory cell has first and second memory sections, and said fist memory section is comprised of said first load IG FET, said first driver IG FET and said second transfer IG FET, while said second memory section is comprised of said second load IG FET, said second driver IG FET and said first transfer IG FET.