Ladder drum sequence controller

• US 5,072,356 A
• Filed: 04/02/1990
• Issued: 12/10/1991
• Est. Priority Date: 04/11/1988
• Status: Expired due to Term

• Current Assignee: Square D Company (Schneider Electric SE)
• Original Assignee: Square D Company (Schneider Electric SE)
• Inventors: Ryan, Richard L., Ksicinski, Charles C., Romanowich, Gary A., Watt, Kim J.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): TRAMMELL, JAMES P
• Application Number:
  US07/504,057
• Time in Patent Office: 617 Days
• Field of Search: 364/136, 364/140, 364/141, 364/146, 364/147, 364/900 MS File, 364/143
• US Class Current: 700/23
• CPC Class Codes: G05B 19/05 Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
• CPC Class Codes: G05B 2219/1151 Fast scanning of I-O to put I-O status in image table
• CPC Class Codes: G05B 2219/1159 Image table, memory
• CPC Class Codes: G05B 2219/13064 Execute reverse sequence
• CPC Class Codes: G05B 2219/15102 Programmer simulates, behaves like a programming drum

Abstract

A drum-type sequencer operable in a ladder logic program and capable of being selectively stepped in various modes; that is, in forward stepped sequence, non-sequentially, and backwardly.

Claims

1. A drum sequence controller for outputting control information to sequentially perform a series to steps based selectively on one of a plurality of valid conditions, said drum sequence controller adapted to thereby control the operation of a plurality of devices over a communications system bus, said drum sequence controller comprising:

a control processor;

a memory including a plurality of registers;

a first plurality of said registers providing configuration table registers, said configuration table registers providing control and status of current step, said configuration table registers include means for incrementing said steps in a forward sequence, and;

said configuration table registers include means for decrementing said steps in a reverse sequence; and

a second plurality of said registers comprising step or table registers, said step or table registers indicating a step increment or decrement based selectively on one of said plurality of valid conditions, said plurality of valid conditions based on time, event, a combination of time and event, or one of time or event, said event being an input, and said step or table registers providing step increments or decrements for a plurality of said steps.

2. The drum sequence controller of claim 1, wherein said configuration table include register means for defining one of said steps which responds to an input or a predetermined time period to control the operation of a plurality of devices.

3. The drum sequence controller of claim 1, wherein said configuration table registers includes a selected size bit register, and said step or table register specifies output data with, from 1 to 64 bits, by utilizing two or more registers.

4. The drum sequence controller of claim 1, wherein the sequence of processable steps is possible for at least 255 steps.

5. A drum sequence controller for outputting control information to sequentially perform a series of steps, each of which consists of an input and an output, said steps selectively based on time, event, a combination of time and event, or one of time or event, the drum sequence controller comprising:

configuration table registers for storing data defining step operating conditions for each of said steps, said step operating conditions data including a number identifying the step currently being performed, sequence operating conditions, total time the current step has been executing, an address of an input from which said event is to be determined, and an address of an output to which said control information is to be sent;

a plurality of sets of step table registers, each of said sets defining one of said steps to be performed;

means responsive to said configuration table registers and said sets of step table registers for selectively executing each of said steps; and

means for executing an out-of-sequence step wherein said configuration table registers include a register operative as a pointer for executing said out-of-sequence step.

6. The drum sequence controller of claim 5, wherein said sequence operating conditions includes data defining whether said sequential performance of said steps shall be incremented forwardly or decremented backwardly.