Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates

• US 5,072,369 A
• Filed: 04/07/1989
• Issued: 12/10/1991
• Est. Priority Date: 04/07/1989
• Status: Expired due to Term

• Current Assignee: Computer Cache Coherency Corporation (Acacia Research Corporation)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Beachy, Jeffrey L., Theus, John G.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): KIM, KENNETH S
• Application Number:
  US07/335,173
• Time in Patent Office: 977 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

An interface circuit permits a first bus master connected to a first bus to directly access a main memory connected to a second bus while maintaining coherency between corresponding data in the main memory and a cache memory used by a second bus master on the second bus. The interface circuit maps selected first bus addresses to corresponding second bus addresses such that when a bus master on the first bus attempts to read or write access one of the mapped first bus addresses, the bus interface circuit responds by read or write accessing a corresponding address in the memory on the second bus. The bus interface circuit stores SNOOP data indicating which memory addresses contain data cached in the cache memory, and when accessing a cached memory address, the bus interface circuit places a signal on the second bus telling the second bus master to copy data from the cache memory into the main memory before the interface circuit performs a main memory read access or to copy data from the main memory to the cache memory after the interface circuit completes a main memory write access, thereby to maintain coherency between the main memory and the cache memory.

Claims

1. An apparatus for providing data communication between first and second buses,

the first bus providing a first plurality of bus masters connected thereto with data read and write access to first data storage locations mapped to separate addresses within a first address space, wherein one of said first plurality of bus masters writes data to a first particular one of said first data storage locations by placing on the first bus an address to which the first particular one of said first data storage locations is mapped and transmitting the data via said first bus, and wherein one of said first plurality of bus masters reads data from a second particular one of said first data storage locations by placing on the first bus an address to which the second particular one of said first storage locations is mapped and receiving data via said first bus,

the second bus providing a second plurality of bus masters connected thereto with data read and write access to second data storage locations mapped to separate addresses within a second address space, wherein one of said second plurality of bus masters writes data to a first particular one of said second data storage locations by placing on the second bus an address to which the first particular one of said second data storage locations is mapped and transmitting the data via said second bus, and wherein one of said second plurality of bus masters reads data from a second particular one of said second data storage locations by placing on the second bus an address to which the second particular one of said second storage locations is mapped and receiving data via said second bus,

wherein one of said second plurality of bus masters connected to said second bus caches data read out of a subset of said second data storage locations, said second bus including means for conveying a SNOOP signal with an address appearing on the bus, the SNOOP signal telling said one of said second plurality of bus masters when to write cached data to the address appearing on the bus,

the apparatus comprising:

first mapping means coupled to said first bus for mapping first addresses within the first address space to second addresses within the second address space, for asserting an indicating signal and for generating one of said second addresses in response to one of said first addresses transmitted on said first bus from one of said first plurality of bus masters, said first mapping means also generating a SNOOP signal of a state indicating when a generated second address is mapped to one of said particular subset of the second data storage locations, and

bus interface means connected to said first and second buses for responding to the first indicating signal when said one of said first plurality of bus masters is reading data by placing the generated second address and SNOOP signal on the second bus, receiving data from a second data storage location mapped to said second address, and transmitting the received data to said one of said first plurality of bus masters via said first bus when the said one of said first plurality of bus masters is reading data.

2. The apparatus in accordance with claim 1 wherein said first mapping means generates said second address and said SNOOP signal in accordance with adjustable address mapping and SNOOP data stored by said mapping means.

3. The apparatus in accordance with claim 2 wherein said bus interface means further comprises means permitting one of said second plurality of bus masters connected to the second bus to adjust said mapping data and said SNOOP data by write accessing a portion of said second address space via said second bus.