Real-time data processing system

• US 5,072,373 A
• Filed: 01/17/1991
• Issued: 12/10/1991
• Est. Priority Date: 03/10/1984
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Encore Computer Corp. (Transdigm Group Incorporated)
• Inventors: Dann, James C.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US07/642,457
• Time in Patent Office: 327 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 709/201
• CPC Class Codes: G06F 15/161 Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning casings, cabinets, racks or drawers for data centers H05K5/00
• CPC Class Codes: G06T 15/005 General purpose rendering architectures

Abstract

A real time data processing system in which each of a series of processing nodes is provided with its own data store partitioned into a first section reserved for the storage of data local to the respective node and a second section reserved for the storage of data to be shared between nodes. The nodes are interconnected by a data link and whenever a node writes to an address in the second section of a data store the written data is communicated to all of the nodes via the data link. The data in each address of the second sections of the data stores can be changed only by one respective processing node which acts as a master for that address. As each address containing shared data can only be written to by one node collisions between different nodes attempting to change a common item of data cannot occur.

Claims

1. A method of reflecting data among a plurality of processing nodes interconnected through a reflective data link, comprising the steps of:

establishing for each node a memory having a first data port and a second data port and having a set of addresses;

establishing for each node processing means connected to said first data port of the associated memory for reading data from said memory and for writing data into said memory;

sensing write data from the processing means of a node to the first data port of the associated memory that is being written into preselected addresses of said associated memory, and

forwarding said sensed write data directly into said data link for reflection into the memories of other processing nodes interconnected through the data link,

sensing write data on said data link being written into preselected addresses of memory, and

forwarding said sensed write data from said data link directly into the associated memory of a node through the second data port of the memory.

2. The method according to claim 1 including the further step of directing the sensed write data from said data link into correlated addresses in the associated memory of a node.

3. The method according to claim 1 including the further step of controlling a portion of said set of data addresses for a memory of a node wherein data for said portion of said set of data addresses can only be written by the associated processing means.

4. The method according to claim 1 including the further step of forwarding the sensed write data from the processing means of a node directly to a second reflective data link connected in parallel to the first mentioned reflective data link.

5. The method as defined in claim 1, wherein the preselected addresses are independently selectable for controlling each sensing of write data from the processing means of the nodes.

6. The method as defined in claim 1 wherein the preselected addresses are independently selectable for each node for controlling sensing of write data on said data link.

7. The method of claim 1 including the further steps of partitioning each memory into a local section and a shared section and controlling each sensing of write data from the processing means to the associated memory to forward a sensed write to the data link only if it is being written to an address in said shared section.

8. A method of reflecting data among a plurality of processing nodes interconnected through a data link, comprising the steps of:

establishing for each processing node a memory having a first data port and a second data port and having a set of addresses;

establishing for each node processing means connected to said first data port of said memory for reading data from said memory and for writing data into said memory;

establishing a sense logic means for each processing node connected to said processing means, said second data port of said memory and the data link for sensing write data being written into preselected addresses of memory;

setting a first predetermined range of memory addresses in each of said sense logic means;

sensing write transfers being written into the memories;

comparing each of the sensed write transfers to determine if said sensed write transfer is being written to an address within said first predetermined range of memory addresses;

receiving and queuing sensed and compared write transfers that are written to addresses within said first predetermined range of memory addresses;

transmitting queued sensed write transfers from said first queuing means onto said data link independently of said processing means;

sensing a write transfer on the data link;

setting a second predetermined range of memory addresses in said sense logic means;

comparing a sensed write transfer sensed on the data link to determine if said sensed write transfer is written to an address within said second predetermined range of memory addresses; and

queuing sensed write transfers that are written to addresses within said second predetermined range of memory addresses and releasing them into the second port of the memory independently of said processing means.

9. A method of reflecting data among a plurality of processing nodes interconnected through a data link comprising the steps of:

establishing for each node a memory having at least two data ports and having a set of addresses;

establishing for each node processing means connected to one data port of said memory for reading data from said memory and for writing data into said memory;

establishing for each node write sense logic means connected to said processing means and the other data port of said memory for sensing write data being written into preselected addresses of said memory, for forwarding said sensed write data via said data link to other processing units interconnected through the data link and for passing data on said data link to said other port of said memory;

setting a first predetermined range of memory addresses in each said write sense logic means;

sensing a write transfer being written to a memory;

comparing a sensed write transfer to determine if said sensed write transfer is being written to an address within said first predetermined range of memory addresses of the memory;

receiving and queuing sensed compared write transfers that are written to addresses within said first predetermined range of memory addresses; and

transmitting queued sensed write transfers onto said data link independently of said processing means of said processing node.

10. The method of claim 9 including the further steps of:

establishing read sense logic means for sensing data on said data link and forwarding data having predetermined addresses to memory via said second data port;

setting a second predetermined range of memory addresses in said read sensing logic means;

sensing a write transfer on the data link;

comparing a sensed write transfer on the data link to determine if said sensed write transfer is written to an address within said second predetermined range of memory addresses; and

queuing sensed compared write transfers that are written to addresses within said second predetermined range of memory addresses and releasing them into the second data port of memory of the associated processing node independently of the processing means of said processing node.

11. A method of reflecting data between a first processing node and a second processing node via a reflective data link connected between said first processing node and said second processing node for transferring data therebetween comprising the steps of:

(a) establishing a first processing node having a first processor and a first dual data port memory;

(b) processing data and writing processed data into one port of said first dual data port memory, said processed data being in one of a local category and a shared category;

(c) sensing a write from said first processor into said one port of said first dual data port memory;

(d) discriminating if said sensed write is being written to a first predetermined range of memory addresses;

(e) transmitting onto said reflective data link a sensed write being written to an addresses within said first predetermined range of memory addresses;

(f) establishing a second processing node having a second processor and a second dual data port memory;

(g) processing data and writing processed data into one port of said second dual data port memory, said processed data being in one of a local category and a shared category;

(h) sensing a write from said second processor into said one port of said second dual data port memory;

(i) discriminating if said sensed write is being written to a second predetermined range of memory addresses;

(j) transmitting onto said reflective data link a sensed write being written to an address within said second predetermined range of memory addresses;

(k) sensing a write on the reflective data link; and

(l) controlling said write sensed on the reflective data link to determine the address to which is being written, and responsive thereto releasing same into the second port of at least one of said memories.

12. The method according to claim 11 including the further steps of:

(a) establishing a third processing node having a third processor and a third dual data port memory;

(b) processing data and writing processed data into one port of said third dual data port memory, said processed data being in one of a local category and a shared category;

(c) sensing a write from said third processor into said one port of said third dual data port memory;

(d) discriminating if said sensed write is being written to a third predetermined range of memory addresses; and

(e) transmitting onto said reflective data link a sensed write being written to an address within said third predetermined range of memory addresses.

13. The method of claim 12 including the further steps of:

(a) establishing a fourth processing node having a fourth processor and a fourth dual data port memory;

(b) processing data and writing processed data into one port of said fourth memory, said processed data being in one of a local category and a shared category;

(c) sensing a write from said fourth processor into said one port of said fourth dual data port memory;

(d) discriminating if said sensed write is being written to a fourth predetermined range of memory addresses;

(e) transmitting onto said reflective data link a sensed write being written to an address within said fourth predetermined range of memory addresses; and

(f) establishing a second reflective data link connected between said first processing node and said third processing node for transferring data therebetween.

14. The method of claim 13 including the further step of establishing a third reflective data link connected between said second processing node and said fourth processing node for transferring data therebetween.

15. The method of claim 14 including the further step of establishing a fourth reflective data link connected between said third processing node and said fourth processing node for transferring data therebetween.

16. A method of real-time data processing comprising the steps of:

(a) establishing a plurality of processing nodes, each including;

a bus for carrying information;

a processor for processing information connected to the bus means and putting write transfers on the bus means; and

a memory for storing information having a port connected to the bus and including means for accepting through its port a write transfer on the bus means as transferred from the processor;

(b) establishing a write only reflective data link for transferring information containing writes between the plurality of processing nodes;

(c) sensing a write transfer on a bus intended for its associated memory;

(d) setting a first predetermined range of memory addresses;

(e) comparing a sensed write transfer to determine if said sensed write transfer is being written to an address within said first predetermined range of memory addresses;

(f) queuing sensed write transfers that are written to addresses within said first predetermined range of memory addresses; and

(g) transmitting queued sensed write transfers onto said reflective data link independently of its said associated processor.

17. The method of claim 16 including the further steps of:

(a) establishing the memory of each processing node with a second port;

(b) sensing a write transfer on the write only reflective data link; and

(c) transferring a sensed write transfer on the write only reflective data link into the second port of a memory of a processing node without intervention of the associated processor of any processing nodes.

18. The method of claim 17 including the further steps of:

(a) setting a second predetermined range of memory addresses;

(b) comparing a sensed write transfer sensed on the reflective data link to determine if said sensed write transfer is written to an address within said second predetermined range of memory addresses;

(c) queuing sensed write transfers that are written to addresses within said second predetermined range of memory addresses; and

(d) releasing a queued sensed write transfer into the second port of a memory of a processing node independently of any processor of a processing node.

19. The method of claim 18 wherein the predetermined ranges of memory addresses are independently selectable.

20. The method of claim 19 including the further steps of partitioning each memory into a local section and a shared section, and transferring a sensed write transfer onto the write only reflective data link only if it is written to an address in the shared section of the memory of at least one processing node.

21. The method of claim 20 wherein each node has its own unique address partition in its memory so that only one node is capable of writing data to any one address in the shared data sections of the memory.

22. The method of claim 18 wherein the predetermined ranges of memory addresses are independently predetermined.

23. The method of claim 16 wherein the write only reflective data link is a bus.

24. A method comprising the steps of:

(a) providing a processing node and a reflective data link, said processing node located in a processing system interconnected to other processing units through the reflective data link;

(b) providing for said processing node a memory having a first data port and a second data port and having a set of addresses and a processor connected to said first data port of said memory for reading data from said memory and for writing data into said memory;

(c) sensing a write from said processor into said one port of said memory;

(d) determining if said sensed write is being written to a first predetermined range of memory addresses;

(e) transmitting onto said reflective data link a sensed write being written to an address in said first predetermined range of memory addresses;

(f) sensing a write on the reflective data link;

(g) determining if said write sensed on the reflective data link is being written to a second predetermined range of memory addresses; and

(h) releasing same into the second port of said memory responsive thereto.

25. A method including the steps of:

(a) providing a data processing system including a plurality of processing nodes and a reflective data link for transferring write only data between the processing nodes;

(b) providing each processing node with a memory having two data ports and a processor connected to one port of said memory;

(c) sensing a write from a processor into one port of its associated memory;

(d) determining if said sensed write is being written to a first predetermined range of memory addresses;

(e) transmitting onto said reflective data link a sensed write being written to an address in said first predetermined range of memory addresses;

(f) sensing a write on the reflective data link;

(g) determining if said write sensed on the reflective data link is being written to a second predetermined range of memory addresses; and

(h) releasing same into the second port of said memory responsive thereto.

26. The method according to claim 25 wherein the processor of at least one said processing node is master of a portion of said predetermined set of addresses wherein data for said portion of said predetermined set of addresses can only be written by said processor.

27. The method of claim 25 including the further step of connecting the processor of each node to its associated memory via a bus.