Series maxium/minimum function computing devices, systems and methods

• US 5,072,418 A
• Filed: 05/04/1989
• Issued: 12/10/1991
• Est. Priority Date: 05/04/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Boutaud, Frederic, Ehlig, Peter N.
• Primary Examiner(s): Shaw, Dale M.
• Application Number:
  US07/347,596
• Time in Patent Office: 950 Days
• Field of Search: 340/146.2, 364/715.06, 364/736
• US Class Current: 708/207
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/3652 in-circuit-emulation [ICE] arrangements
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/462 with multiple register sets

Abstract

A data processing device includes an instruction decoder and an arithmetic logic unit having first and second inputs and an output. An accumulator is connected between the output and first input of the arithmetic logic unit. A further register is connected between the accumulator and the second input of the arithmetic logic unit. The arithmetic logic unit includes circuitry for computing a digital value to the accumulator as well as an additional circuit. The additional circuit thereupon compares the value at the second input from said register with the digital value in the accumulator in response to a command from the instruction decoder and then stores to the register the lesser or the greater in value of the contents of the register and the digital value in the accumulator depending on the command. Other devices, systems and methods are also disclosed.

Claims

1. A data processing device comprising:

an instruction decoder;

an arithmetic logic unit having first and second inputs and an output;

an accumulator connected between the output and first input of said arithmetic logic unit; and

a register connected between said accumulator and the second input of the arithmetic logic unit, said arithmetic logic unit for computing a digital value to said accumulator and thereupon comparing the value at the second input from said register with the digital value in said accumulator in response to a command from the instruction decoder and then storing to said register the lesser or greater in value of the contents of said register and the digital value in said accumulator depending on the command.

2. The data processing device of claim 1 wherein said arithmetic logic unit includes a multiplexing circuit to select the contents of the register or an independent digital signal for said second input.

3. The data processing device of claim 1 wherein repeated execution of the command upon each of a series of arithmetic values supplied over time to said accumulator supplies the register with the minimum or maximum value in the series of arithmetic values, depending on the command.

4. The data processing device of claim 1 wherein said register has a width in bits equal to the width in bits of the accumulator.

5. The data processing device of claim 1 wherein the register is stored to the accumulator or the accumulator to the register depending on the lesser or greater determination.

6. The data processing device of claim 1 wherein comparing and storing includes computing in a subtraction mode and then storing in accordance with the sign of the arithmetic difference between the contents of said register and the digital value in said accumulator.

7. The data processing device of claim 1 further comprising a prescaling shifter selectively connected to said arithmetic logic unit.

8. The data processing device of claim 7 further comprising a data memory and a data bus connecting said data memory to said prescaling shifter.

9. The data processing device of claim 8 wherein said prescaling shifter includes a multiplexing circuit to selectively connect said prescaling shifter to said data bus or to said accumulator.

10. The data processing device of claim 8 further comprising a multiplier connected to said data bus wherein said arithmetic logic unit includes circuitry for selecting any one of said prescaling shifter, said register, or said multiplier to said second input.

11. The data processing device of claim 8 further comprising a post scaling shifter connected between said accumulator and said data bus.

12. The data processing device of claim 1 further comprising a program address bus, a program counter, a program memory connected to said program counter by said program address bus, and a program data bus, the program memory connected by said program data bus to supply instructions to said decoder.

13. A data processing device, comprising:

a data memory and a data bus connected to said data memory;

arithmetic logic circuitry for electronically producing digital signals representing computed arithmetic values, the arithmetic values over time having a maximum value, said arithmetic logic circuitry having an output, a first input and a second input;

an accumulator having an input connected to said output of said arithmetic logic circuitry and having an accumulator output connected to the first input of said arithmetic logic circuitry;

an accumulator buffer connected to said accumulator for selective bidirectional transfers therebetween; and

circuitry for selectively coupling said first input of said arithmetic logic circuitry to said accumulator buffer or to said data bus, said arithmetic logic circuitry responsive to an instruction for comparing the contents of said accumulator via said first input with the contents of said accumulator buffer via said second input and then transferring a value in the accumulator to said accumulator buffer when a value in said accumulator buffer is less than the value in the accumulator.

14. The data processing device of claim 13 wherein repeated execution of the instruction when each of a series of arithmetic values is supplied to the accumulator supplies the accumulator buffer with the maximum value in the series of the arithmetic values.

15. The data processing device of claim 13 wherein said arithmetic logic circuitry is further responsive to the instruction to transfer a value in said accumulator buffer to said accumulator when a value in said accumulator buffer is greater than the value in said accumulator.

16. A signal processing system comprising:

converter means for converting a signal having a varying level from analog to digital form; and

a programmable microcomputer having an instruction decoder, an accumulator and an accumulator buffer, and arithmetic logic unit means for counting an arithmetic difference between a first value representative of the signal in the accumulator with a second value in the accumulator buffer and then storing in response to said instruction decoder the first value into the accumulator buffer when the first value exceeds the second value, and the second value into the accumulator when the second value exceeds the first value, thereby computing a maximum value of the signal, and multiplier means for automatically adjusting a gain value for the signal as a function of the maximum value so computed.

17. The signal processing system of claim 16 further comprising a program memory connected to said instruction decoder, the program memory holding instructions for operating the microcomputer as a bandpass filter for the signal.

18. The signal processing system of claim 16 further comprising a program memory connected to said instruction decoder, the program memory holding instructions for operating the microcomputer as a demodulator for the signal.

19. A signal processing system comprising:

sensor means for producing a digital signal in response to a physical input representative of a pattern;

a programmable microcomputer having an instruction decoder, a first register and a second register, and arithmetic logic unit means for computing an arithmetic difference between a first value representative of the digital signal in the first register and a second value in the second register and then storing in response to said instruction decoder the first value into the second register or the second value into the first register thereby computing a maximum or minimum value of the signal depending on the arithmetic difference and on an instruction type; and

a program memory connected to said microcomputer holding instructions for execution by said microcomputer to recognize the pattern.

20. The signal processing system of claim 19 wherein said sensor means includes a microphone and an analog-to-digital converter and said program memory holds instructions for a speech recognition process.

21. The signal processing system of claim 19 wherein said sensor means includes an optical sensor and said program memory holds instructions for an edge detection process.

22. A method of operating a data processing device including an arithmetic logic unit and accumulator, an additional register, and a multiplexer, comprising the steps of:

supplying digital signals representative of numerical values to said arithmetic logic unit and thereupon storing a digital signal in the accumulator representing the result of an arithmetic operation on the numerical values performed by the arithmetic logic unit; and

on a command that represents a greater-than or less-than instruction, operating said multiplexer to select the contents of the additional register, operating the arithmetic logic unit to compare the contents of the accumulator and the additional register and then transferring the greater or lesser numerical value represented by the contents and in accordance with the command between the accumulator and the additional register.

23. The method of claim 22 further comprising the steps of repeatedly operating the multiplexer and coactively operating the arithmetic logic unit upon each of a series of arithmetic values supplied over time to said accumulator thereby supplying the maximum or minimum value in the series of values.

24. A data processing apparatus comprising:

an arithmetic logic unit having first and second data inputs and an output;

a first register connected to the first data input and to the output of said arithmetic logic unit; and

a second register connected between said first register and the second input of said arithmetic logic unit, wherein a signal from said arithmetic logic unit determined from a signal of a difference in value between said firs register and said second register selectively stores to said second register a value from said first register depending on whether the value in said first register is greater or lesser than a value in said second register.

25. The data processing apparatus of claim 24 further comprising an instruction decoder connected to write a value from said second register into said first register.

26. A data processing system comprising:

an input device operative to produce a digital signal in response to a physical input representative of a pattern;

a computer device connected to said input device having;

an arithmetic logic unit having first and second data inputs and an output;

a first register connected to the first data input and to the output of said arithmetic logic unit; and

a second register connected between said first register and the second input of said arithmetic logic unit, wherein a signal from said arithmetic logic unit determined from a difference in value between said first register and said second register stores to said second register a value from said first register; and

an output device connected to said computing device.

27. The data processing system of claim 26 wherein said input device includes an analog-to-digital converter and said output device includes an amplifier.

28. The data processing system of claim 26 wherein said input device includes a host computer and said output device includes a color palette and display interface.