Apparatus comprising an electrostatic wafer cassette

• US 5,073,716 A
• Filed: 12/12/1990
• Issued: 12/17/1991
• Est. Priority Date: 05/10/1990
• Status: Expired due to Term

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Original Assignee: AT&T, Inc.
• Inventors: Hong, Shane Y., Clemens, James T.
• Primary Examiner(s): Berman, Jack I.
• Application Number:
  US07/626,930
• Time in Patent Office: 370 Days
• Field of Search: 250/492.2, 250/492.3, 250/398, 250/492.21, 250/440.1, 250/453.1, 361/234
• US Class Current: 250/492.2
• CPC Class Codes: H01J 37/20 Means for supporting or positioning the objects or the material; Means for adjusting diaphragms or lenses associated with the support introducing the objects H01J37/18
• CPC Class Codes: H01L 21/67386 characterised by the construction of the closed carrier
• CPC Class Codes: H01L 21/6831 using electrostatic chucks
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks

Abstract

Disclosed is apparatus comprising an electrostatic cassette assembly for securing a semiconductor wafer during lithographic processing such as direct-write particle-beam lithography. The cassette assembly comprises a cassette body and an electrostatic chuck installable in, and removeable from, the cassette body. The electrostatic chuck comprises a charge plate having a thin dielectric layer on its upper surface, against which the wafer is flattened by Coulombic force. Charge storage means are included for maintaining an electrical potential difference between the wafer and the charge plate even in the absence of connection to a source of electrical energy external to the assembly.

Claims

1. A method for manufacturing an article, comprising the steps of:

providing a semiconductor wafer having first and second major surfaces and a processing layer overlying at least a portion of the first surface;

providing means for securing the wafer, the securing means including a charge plate;

electrostatically flattening the wafer against the charge plate;

exposing the processing layer to actinic radiation; and

performing at least one additional step toward completion of the article,

CHARACTERIZED IN THAT

the securing means further comprise means for storing an electrical charge, the charge storage means being adapted to maintain an electrical potential difference, without connection to a source of electrical energy external to the securing means, for a period of time that is longer than an average exposure time associated with said exposing step; and

the flattening step comprises the steps of creating an electrical potential difference between the wafer and the charge plate, and maintaining the potential difference by means of the charge storage means.

2. The method of claim 1, wherein the charge storage means comprise at least one electrical battery.

3. The method of claim 1, wherein the charge storage means comprise at least one electrical capacitor, and the flattening step further comprises charging the capacitor.

4. The method of claim 1, wherein the charge storage means have first and second terminals of opposite polarity, the first terminal is capable of being electrically connected to the charge plate, and the flattening step further comprises electrically connecting the second terminal to the wafer.