Method of coplanar integration of semiconductor IC devices

• US 5,075,253 A
• Filed: 09/12/1990
• Issued: 12/24/1991
• Est. Priority Date: 04/12/1989
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sliwa, John W. Jr.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Hugo, Gordon V.
• Application Number:
  US07/581,510
• Time in Patent Office: 468 Days
• Field of Search: 437/209, 437/211, 437/51, 437/208, 437/915, 437/90, 357/75
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/95146 by surface tension
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A high degree of wafer-scale integration of normally incompatible IC devices is achieved by providing a plurality of segments (10), each segment having thereon one or more circuits, circuit elements, sensors and/or I/O connections (14'"'"'). Each segment is provided with at least one edge (12) having an abutting portion (12a) capable of abutting against a similar edge of a neighboring segment. The segments are placed on the surface of a flotation liquid (20) and are allowed to be pulled together so as to mate abutting edges of neighboring segments, thereby forming superchips (10'"'"'). Microbridges (22) are formed between neighboring segments, such as by solidifying the flotation liquid, and interconnections (26) are formed between neighboring segments. In this manner, coplanar integration of semiconductor ICs is obtained, permitting mixed and normally incompatible circuit functions on one pseudomonolithic device as diverse as silicon and III-V digital circuits, III-V optoelectronic devices, static RAMs, charge coupled devices, III-V lasers, superconducting thin films, ferromagnetic non-volatile memories, high electron mobility transistors, and bubble memories, to name a few, to be integrated in any desired combination. The yieldable scale of integration of a given device technology is also greatly extended. The segments are brought together in a particulate-free fashion with high throughput and exacting reproducibility at low cost.

Claims

1. A method for coplanar integration of semiconductor IC devices comprising:

(a) providing at least segments, each having at least one edge having an abutting portion capable of abutting against a similar edge of a neighboring segment, each segment having on a top surface thereof at least one of the items selected from the group consisting of circuits, circuit elements, sensors, and input/output connections;

(b) providing a mother substrate having openings formed therein to accept said segments in stacked array;

(c) placing said segments in said openings in said mother substrate; and

(d) forming electrical interconnections between neighboring segments so as to interconnect various of said circuits, circuit elements, sensors, and input/output connections.

2. The method of claim 1 wherein said segments are mechanically secured in said openings by a solid microbridge.

3. The method of claim 2 wherein said solid microbridge is formed by introducing a liquid between said segments and between said segments and said substrate and treated to form said solid microbridge.

4. The method of claim 3 wherein said microbridge material is characterized by the properties of semiconductor electronic-grade ionic and particulate cleanliness and is a dielectric.

5. The method of claim 4 wherein said microbridge material is selected from the group consisting of polyimides, polyimide precursors, epoxies, UV- and heat-curable polymers, and silica.

6. The method of claim 1 wherein said electrical interconnections include selective tungsten.

7. The method of claim 6 wherein said segments and said substrate are provided with edge contacts, a portion of which edge contacts is trenched into said segments and said substrate along an edge thereof and said electrical interconnections include interconnecting edge contacts on said segments and on said substrate.

8. The method of claim 1 wherein said segments are placed on one edge in said openings to expose an upper edge thereof and at least some of said electrical interconnections are formed along said upper edges.