Phase locked loop circuit responding to supplied signal frequency

• US 5,075,640 A
• Filed: 03/06/1991
• Issued: 12/24/1991
• Est. Priority Date: 03/09/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Miyazawa, Yuichi
• Primary Examiner(s): Pascal, Robert J.
• Application Number:
  US07/665,248
• Time in Patent Office: 293 Days
• Field of Search: 331/10, 331/25, 331/34, 331/57
• US Class Current: 331/10
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

A phase locked loop circuit, which is arranged for receiving a first signal having a given frequency and producing a second signal which has the same frequency and is synchronous with the first signal, comprises control voltage generating means for generating a control voltage responding to a phase difference and a frequency difference between the first and second signals, a voltage controlled oscillator containing a ring oscillator having a multiplicity of the rows of inverters for producing a frequency output which is primarily determined by the control voltage, and a quantity-of-rows changing means for automatically changing the quantity of the inverters rows in the ring oscillator according to the control voltage.

Claims

1. A phase locked loop circuit, said circuit arranged for receiving a first signal having a given frequency and producing a second signal which has the same frequency and is synchronous with the first signal, comprising:

control voltage generating means for generating a control voltage responding to a phase difference and a frequency difference between the first and second signals;

a voltage controlled oscillator containing a ring oscillator having a multiplicity of quantities of the inverters rows for producing a frequency output which is determined by the control voltage; and

a quantity-of-rows changing means for automatically changing the quantity of the inverters rows in the ring oscillator responding to the control voltage.

2. A phase locked loop circuit according to claim 1, wherein said control voltage generating means comprises:

a phase comparator for producing through comparing the first signal with the second signal fed back from the output a pulse of a phase difference signal between the first and second signals;

a charge pump for converting the phase difference signal pulse into a current pulse;

a lowpass filter for converting the current pulse into a DC voltage;

said voltage controlled oscillator containing a ring oscillator having an odd number of quantity of the inverters rows coupled in cascade for producing the second signal having said frequency when receiving the control voltage; and

said quantity of rows selector being arranged for automatically selecting a quantity of the inverters rows in the ring oscillator according to the control voltage.

3. A phase locked loop circuit according to claim 2, wherein said phase comparator produces through comparing between the first and second signals an UP and a DOWN signal carrying information about a phase difference.

4. A phase locked loop circuit according to claim 2, wherein said charge pump contains an inverter.

5. A phase locked loop circuit according to claim 2, wherein said lowpass filter contains a capacitor and a resistor.

6. A phase locked loop circuit according to claim 1, further comprising a divider for dividing by an integer the second signal received to a divided output which is then fed to the phase comparator.

7. A phase locked loop circuit according to claim 6, wherein said divider contains a D-type flip-flop.

8. A phase locked loop circuit according to claim 1, wherein said quantity of inverters rows selector is arranged to feed an output from the inverter of a given row in the ring oscillator back to the input of the first row of the ring oscillator in response to the control voltage.

9. A phase locked loop circuit according to claim 8, wherein said quantity of inverters rows selector contains a first current mirror circuit for comparing the control voltage with a first reference potential and a second current mirror circuit for comparing the control voltage with a second reference potential which is lower than the first reference potential so that the quantity of the inverters rows can automatically be changed according to a result from the comparison.

10. A phase locked loop circuit according to claim 3, further comprising a synchronism detector provided between the output of the phase comparator and the quantity of inverters rows selector for judging whether synchronization is detected or not upon receiving UP and DOWN signals from the phase comparator, and if synchronization is detected, feeding to the quantity of inverters rows selector a stop signal for stopping the change of the quantity of the inverters rows.

11. A phase locked loop circuit according to claim 3, further comprising a synchronism detector provided between the lowpass filter and the quantity of inverters rows selector for judging whether synchronization is detected or not upon receiving the control signal from the lowpass filter and if synchronization is detected, feeding to the quantity of inverters rows selector a stop signal for stopping the change of the quantity of the inverters rows.

12. A phase locked loop circuit according to claim 10, wherein said synchronism detector contains one of 2-bit noncycling counter for accepting the UP signal from the phase comparator as a clock input and the DOWN signal as a reset input, and another counter for accepting the UP signal as reset input and DOWN signal as a clock input.

13. A phase locked loop circuit according to claim 1, wherein said quantity of inverters rows selector is arranged to select two or more different quantity of the inverters rows in the ring oscillator according to a value of the control voltage.

14. A phase locked loop circuit according to claim 13, wherein said quantity of inverters rows selector contains a couple of current mirror circuits for receiving the control voltage, an up-down counter for counting the outputs of the current mirror circuits for providing a count output, and a decoder for decoding the count output to produce a decoder output by which more than two different quantities of the inverters rows in the ring oscillator are selected.

15. A phase locked loop circuit according to claim 14, wherein said decoder is arranged to deliver an 8-bit signal to the quantity of inverters rows selector which in turn selects one from eight kinds of quantities of the inverters rows in the ring oscillator.

16. A phase locked loop circuit said circuit arranged for receiving a first signal having a given frequency and producing a second signal which has the same frequency and is synchronous with the first signal, comprising:

control voltage generating means for generating a control voltage responding to a phase difference and a frequency difference between the first and second signals;

a voltage controlled oscillator containing a ring oscillator having a multiplicity of quantities of inverters rows for producing a frequency output which is determined by the control voltage;

a quantity-of-rows changing means for automatically changing the quantity number of the inverters rows in the ring oscillator responding to the control voltage;

a divider for dividing by an integer the second signal supplied to a divided output which is then fed to the phase comparator;

said control voltage generating means comprising a phase comparator for producing through comparing the first signal with the second signal fed back from the output a pulse of a phase difference signal between the first and second signals, a charge pump for converting the phase difference signal pulse into a current pulse, and a lowpass filter for converting the current pulse into a DC voltage;

said voltage controlled oscillator containing a ring oscillator having an odd number of quantity of inverters rows coupled in cascade for producing the second signal having said frequency when receiving the control voltage; and

said quantity of rows selector being arranged for automatically selecting a quantity of the inverters rows in the ring oscillator according to the control voltage.

17. A phase locked loop circuit, said circuit arranged for receiving a first signal having a given frequency and producing a second signal which has the same frequency and is synchronous with the first signal, comprising:

control voltage generating means for generating a control voltage responding to a phase difference and a frequency difference between the first and second signals;

a voltage controlled oscillator containing a ring oscillator having a multiplicity of the quantities of inverters rows for producing a frequency output which is primarily determined by the control voltage;

a quantity-of-rows changing means for automatically changing the quantity of the inverters rows in the ring oscillator responding to the control voltage;

a divider for dividing by an integer the second signal supplied to a divided output which is then fed to the phase comparator;

said control voltage generating means comprising a phase comparator for producing through comparing the first signal with the second signal fed back from the output a pulse of a phase difference signal between the first and second signals, a charge pump for converting the phase difference signal pulse into a current pulse, and a lowpass filter for converting the current pulse into a DC voltage;

said voltage controlled oscillator containing a ring oscillator having an odd number of quantity of inverters rows coupled in cascade for producing the second signal having said frequency when receiving the control voltage; and

said quantity of rows selector being arranged for receiving the control voltage and automatically selecting a quantity of the inverters rows in the ring oscillator according to the said frequency by means of feedback of an output from the inverter of a given row in the ring oscillator to the input of the first row of the ring oscillator.

18. A phase locked loop circuit, said circuit arranged for receiving a first signal having a given frequency and producing a second signal which has the same frequency and is synchronous with the first signal, comprising:

control voltage generating means for generating a control voltage presenting a phase difference and frequency difference between the first and second signals;

a voltage controlled oscillator containing a ring oscillator having a multiplicity of quantities of the inverters rows for producing a frequency output which is determined by the control voltage;

a quantity-of-rows changing means for automatically changing the quantity of the inverters rows in the ring oscillator responding to the control voltage;

a divider for dividing by an integer the second signal supplied to a divided output which is then fed to the phase comparator;

a synchronism detector interposed between the output of the phase comparator and the quantity of inverters rows selector for judging whether synchronization is detected or not upon receiving UP and DOWN signals from the phase comparator and if synchronization is detected, feeding to the quantity of rows selector a stop signal for stopping the change of the quantity of the inverters rows;

said control voltage generating means comprising a phase comparator for producing through comparing the first signal with the second signal fed back from the output a pulse of a phase difference signal between the first and second signals, a charge pump for converting the phase difference signal pulse into a current pulse, and a lowpass filter for converting the current pulse into a DC voltage;

said voltage controlled oscillator containing a ring oscillator having an odd number of quantity of inverters rows coupled in cascade for producing the second signal having said frequency when receiving the control voltage; and

said quantity of inverters rows selector being arranged for receiving the control voltage and automatically selecting a quantity of the inverters rows in the ring oscillator according to said frequency by means of feedback of an output from the inverter of a given row in the ring oscillator to the input of the first row of the ring oscillator.