Two-transistor programmable memory cell with a vertical floating gate transistor

• US 5,078,498 A
• Filed: 06/29/1990
• Issued: 01/07/1992
• Est. Priority Date: 06/29/1990
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Mori, Kiyoshi, Kadakia, Shailesh R.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Crane, Sara W.
• Application Number:
  US07/546,065
• Time in Patent Office: 557 Days
• Field of Search: 357/23.6 G, 357/23.4, 357/23.5, 357/23.6 G, 365/185
• US Class Current: 257/330
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A two-transistor programmable memory cell (FIG. 1A, 20) with one vertical floating gate transistor (VT) and one planar transistor (PT)--the planar transistor can be optimized for programming with low current (longer channel length and narrower channel width), while the vertical transistor can be optimized for reading with high current (shorter channel length and wider channel width). The vertical transistor is formed in a trench (22) with a source region (15) and a sub-source VT drain region (23). The planar transistor includes the source region (15) and a co-planar PT drain region (27).

Claims

1. A two-transistor programmable memory cell, with one vertical floating gate transistor, formed in a substrate of a first conductivity type, comprising:

a vertical transistor including a source region and a sub-source VT drain region vertically disposed in the substrate adjacent a trench, defining a VT channel region of a selected VT channel length in the vertical dimension and a channel width around the trench;

a planar transistor including said source region and a co-planar PT drain region, defining a PT channel region with a selected PT channel length in the planar dimension;

a VT floating gate conductor insulatively disposed in said trench, over said VT channel region;

a PT floating gate conductor insulatively disposed over said PT channel region;

a VT program gate conductor insulatively disposed over said VT floating gate; and

a PT program gate conductor insulatively disposed over said PT floating gate.

2. The two-transistor programmable memory cell of claim 1, wherein:

the VT channel length is selected such that the vertical transistor is characterized by a relatively higher current capacity; and

the PT channel length is selected such that the planar transistor is characterized by a relatively lower current capacity.

3. The two-transistor programmable memory cell of claim 1, wherein said VT floating gate and said PT floating gate comprise segments of a single floating gate.

4. The two-transistor programmable memory cell of claim 3, wherein said VT program gate and said PT floating gate comprise segments of a single program gate.

5. The two-transistor programmable memory cell of claim 1, wherein for each trench said VT floating gate is disposed around the walls of the trench defining a central hole, and said VT program gate is disposed into the hole, thereby maximizing the program gate voltage required to charge the floating gate.

6. The two-transistor programmable memory cell of claim 5, wherein said trench is substantially square.

7. The two-transistor programmable memory cell of claim 1, wherein said trench is surrounded by said source and VT drain regions.

8. The two-transistor programmable memory cell of claim 1, wherein the substrate is P-type and said source and VT and PT drain regions are doped N-type.

9. A two-transistor programmable memory cell, with one vertical floating gate transistor, formed in a substrate of a first conductivity type, comprising:

a source region of a second conductivity type formed in said substrate;

a sub-source VT channel region of the first conductivity type, formed under said source region, with a selected VT channel length in the vertical dimension;

a sub-channel VT drain region of the second conductivity type formed under said VT channel region;

a co-planar PT channel region of the first conductivity type formed in the substrate adjacent said source region with a selected PT channel length in the planar dimension;

a co-planar PT drain channel region of the second conductivity type formed in the substrate adjacent said PT channel region;

a trench area of a selected configuration formed in the substrate extending through said source and VT channel regions and at least partially into said VT drain region;

such that said source region and said VT drain region together with said VT channel region define a vertical transistor with a selected channel length, and said source region and said PT drain region together with said PT channel region form a planar transistor with a selected channel length;

a floating gate conductor having a VT segment insulatively disposed vertically into the trench and a PT segment extending over the PT channel region and at least a portion of the PT drain region, such that the VT segment of said floating gate is capacitively coupled to said VT channel region and the PT segment of said floating gate is capacitively coupled to said PT channel region; and

a program gate insulatively disposed said floating gate;

such that said floating gate and said program gate are common to said vertical and planar transistors.

10. The two-transistor programmable memory cell of claim 9, wherein:

the channel length of said VT channel is selected such that the vertical transistor is characterized by a relatively higher current capacity; and

the channel length of said PT channel is selected such that the planar transistor is characterized by a relatively lower current capacity.

11. The two-transistor programmable memory cell, comprising:

a vertical transistor including a source region and a sub-source VT drain region vertically disposed in a substrate adjacent a sidewall and above a bottom surface of a trench, defining a VT channel region of a selected VT channel length in the vertical dimension and a channel width around the trench; and

a planar transistor including said source region and a coplanar PT drain region, defining a PT channel region with a selected PT channel length in the planar dimension.

12. The device of claim 11, including a VT floating gate conductor insulatively disposed in said trench, over said VT channel region.

13. The device of claim 11, including a PT floating gate conductor insulatively disposed over said PT channel region.

14. The device of claim 12, including a VT program gate conductor insulatively disposed over said VT floating gate.

15. The device of claim 13, including a PT program conductor insulatively disposed over said PT floating gate.