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High speed ECL latch with clock enable

  • US 5,079,452 A
  • Filed: 06/29/1990
  • Issued: 01/07/1992
  • Est. Priority Date: 06/29/1990
  • Status: Expired due to Fees
First Claim
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1. An ECL latch with clock enable, which comprises:

  • a data capture circuit;

    a data latch output circuit coupled to said data capture circuit;

    a first current source coupled to each of said data capture circuit and said data latch output circuit;

    a clock circuit coupled to each of said data capture circuit, said data latch output circuit and said first current source to controllably, periodically gate current from said first current source through one and then the other of said data capture circuit and said data latch output circuit;

    a clock enable circuit having an input and being coupled to said clock circuit to controllably inhibit said clock circuit so that current from said first current source is gated to said data latch output circuit only, when a predetermined enable signal is applied to said input;

    a second current source coupled to each of said clock enable circuit and said data capture circuit; and

    a current switch circuit coupled between said second current source, said clock enable circuit and said data capture circuit to controllably gate current from said second current source to one or the other of said data capture circuit and said clock enable circuit;

    wherein said current switch circuit gates current from said second current source to said clock enable circuit when the predetermined enable signal is applied to said input and gates current from said second current source to said data capture circuit when said clock circuit gates current from said first current source to said data capture circuit.

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