Linearized differential amplifier

• US 5,079,515 A
• Filed: 05/31/1990
• Issued: 01/07/1992
• Est. Priority Date: 05/31/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanimoto, Hiroshi
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/531,798
• Time in Patent Office: 586 Days
• Field of Search: 330/252, 330/256, 330/261, 330/295, 330/149
• US Class Current: 330/256
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 3/45071 with semiconductor devices only

Abstract

Disclosed is a linearized differential amplifier, comprising connecting input terminals and output terminals of the differential pairs respectively in parallel; arranging N sets of differential pairs (where N is an integer of at least 3); an offset voltage generating circuit for supplying different and equivalent offset voltages to the respective differential pairs; a circuit for weighting these output currents; and a circuit for adding the output currents. Particularly, the offset voltage generating circuit and the weighting circuit carry out equivalent weighting of the offset voltages and the output currents so that the change of the differential output current corresponding to the change of the differential input voltage shows an equal ripple characteristic. Moreover, to give equivalent offset voltages to the respective differential pairs, a linearized differential amplifier where emitter areas in respective differential pairs are different is disclosed. In this case, the ratio of emitter areas is 1:7.872983 and 1:1 when N is 3, and 1:13.40261 and 1:2.030215 when N is 4.

Claims

1. A linearized differential amplifier, comprising:

differential pairs of N (N is an integer of at least three) sets arranged in parallel and each comprising bipolar transistors,

means for supplying an equivalent offset voltage to each differential pair;

means for weighting output currents provided from each differential pair; and

means for adding the output current provided from each differential pair,

wherein equivalent offset voltages provided to each differential pair are different from each other.

2. A linearized differential amplifier according to claim 1, wherein

the means for supplying offset voltages and the means for weighting the output currents respectively carry out equivalent weighting of the offset voltages and the output currents so that a change of the output current provided from each differential pair corresponding to a change of an input voltage inputted to the linearized amplifier exhibits a flat characteristic.

3. A linearized differential amplifier according to claim 2, wherein

the output currents to be weighted by the means for weighting have current values of current sources connected to respective emitters commonly connected in the N sets of differential paris.

4. A linearized differential amplifier according to claim 3, wherein

the number of the N sets of differential pairs is four, and the equivalent offset voltages to be provided to the four sets of differential pairs are respectively near to:

1.298·

2·

V_T for the first differential pair;

0.354·

2·

V_T for the second differential pair;

-0.354·

2·

V_T for the third differential pair; and

-1.298·

2·

V_T for the fourth differential pair

(where V_T is the thermal voltage expressed by the equation;

V_T =kT/q, k=Boltzmann'"'"'s constant, T=absolute temperature, q=electric charge of an electron), and

the ratio of weighting the output currents of the first to the fourth differential pair is about 1;

0.5478;

0.5478;

1.

5. A linearized differential amplifier according to claim 1, wherein

the means for supplying offset voltages and the means for weighting the output currents respectively carry out equivalent weighting of the offset voltages and the output currents so that a change of the output current provided from each differential pair corresponding to a change of a differential input voltage inputted to the linearized amplifier exhibits equal ripple characteristic.

6. A linearized differential amplifier according to claim 5, wherein

the output currents to be weighted by the means for weighting have current values of current sources connected to respective emitters commonly connected in the N sets of differential pairs.

7. A linearized differential amplifier according to claim 1, wherein

the means for supplying different and equivalent offset voltages is effected by selecting emitter areas of transistors which are compositional elements of each differential pair.

8. A linearized differential amplifier according to claim 7, wherein

the number of differential pairs of the N sets is four, and a ratio of the emitter areas of the transistors which make up the differential pairs of the four sets is 1:

13.40261, 1;

2.030215, 2.030215, and 13.40261;

1, respectively.

9. A linearized differential amplifier according to claim 1, wherein

the means for adding the output currents of the differential amplifire pairs is composed of a wired OR by which the output terminals of the differential pairs are connected to each other.

10. A linearized differential amplifier according to claim 1, wherein

the means for weighting the output currents is effected by a changeable transconductance of each differential pair obtained by changing proportionally the operational currents of all of the differential pairs.

11. A linearized differential amplifier according to claim 1, wherein

the bipolar transistors are composed of silicon transistor.

12. A linearized differential amplifier according to claim 1, wherein

the bipolar transistors are composed of silicon heterobipolar transistor.

13. A linearized differential amplifier according to claim 1, wherein

the bipolar transistors are composed of Gallium-Arsenide-heterobipolar transistor.

14. A linearized differential amplifier according to claim 1, wherein

the means for weighting is effected by changing the operational currents of the differential pairs in proportion to the absolute temperature.

15. A linearized differential amplifier according to claim 1, wherein

each differential pair has two input terminals and two output terminals,

the input terminals being connected to the means for supplying the equivalent offset voltage,

the output terminals being connected to the means for adding the output current,

one input terminal in each differential pair being connected to one another,

the other input terminal in each differential pair being connected to one another,

one output terminal in each differential pair being connected to one another, and

the other output terminal in each differential pair being connected to one another.

16. A linearized differential amplifier according to claim 15, wherein

the means for adding the output currents of the differential pairs is composed of a wired OR by which the output terminals of the differential pairs are connected to one another.

17. A linearized differential amplifier, comprising:

differential pairs of three sets arranged in parallel and each comprising bipolar transistors,

means for supplying an equivalent offset voltage to each differential pair;

means for weighting output currents provided from each differential pair; and

means for adding the output currents provided from each differential pair,

wherein the equivalent offset voltages are different from each other.

18. A linearized differential amplifier according to claim 17, wherein

the means for supplying offset voltages and the means for weighting the output currents respectively, carry out equivalent weighting of the offset voltages and the output currents so that a change of the output current provided from each differential pair corresponding to a change of an input voltage inputted to the linearized amplifier shows a flat characteristic.

19. A linearized differential amplifier according to claim 18, wherein

the output currents to be weighted by the means for weighting have current values of current sources connected to respective emitters commonly connected in the three sets of differential pairs.

20. A linearized differential amplifier according to claim 19, wherein

the equivalent offset voltages to be provided to the three sets of differential pairs are respectively near to:

22. A linearized differential amplifier according to claim 17, wherein

the means for supplying offset voltages and the means for weighting the output currents respectively, carry out equivalent weighting of the offset voltages and the output currents so that a change of the output current corresponding to a change of a differential input voltage inputted to the linearized differential amplifier exhibits equal ripple characteristic.

24. A linearized differential amplifier according to claim 17, wherein

the means for supplying different and equivalent offset voltages is effected by selecting emitter areas of transistors which are compositional elements of each differential pair.

26. A linearized differential amplifier according to claim 17, wherein

the means for adding the output currents of the differential pairs is composed of a wired OR by which the output terminals of the differential pairs are connected to each other.

27. A linearized differential amplifier according to claim 17, wherein

the means for weighting the output currents is effected by a changeable transconductance of each differential pair obtained by changing proportionally the operational currents of all of the differential pairs.

28. A linearized differential amplifier according to claim 17, wherein

the bipolar transistors are composed of silicon transistor.

29. A linearized differential amplifier according to claim 17, wherein

the bipolar transistors are composed of silicon-heterobipolar transistor.

30. A linearized differential amplifier according to claim 17, wherein

the bipolar transistors are composed of Gallium-Arsenide-heterobipolar transistor.

31. A linearized differential amplifier according to claim 17, wherein the means for weighting is effected by changing the operational currents of the differential pairs proportional to the absolute temperature.

32. A linearized differential amplifier according to claim 17, wherein

each differential pair has two input terminals and two output terminals,

the input terminals being connected to the means for supplying the equivalent offset voltage,

the output terminals being connected to the means for adding the output current,

one input terminal in each differential pair being connected to one another,

the other input terminal in each differential pair being connected to one another,

one output terminal in each differential pair being connected to one another, and

the other output terminal in each differential pair being connected to one another.

33. A linearized differential amplifier according to claim 31, wherein

the means for adding the output currents of the differential pairs is composed of a wired OR by which the output terminals of the differential pairs are connected to one another.

21. 03·

2·

V_T for the first differential pair;

0.0 for the second differential pair; and

-1.03·

2·

V_T for the third differential pair

(where V_T is the thermal voltage expressed by the equation;

V_T =kT/q, k=Boltzmann'"'"'s constant, T=absolute temperature, q=electric charge of an electron), and

the ratio of weighting the output currents of the first and the third differential pair to the second differential pair is about 0.64 times.

23. A linearized differential amplifier according to claim 21, wherein

the output currents to be weighted by the means for weighting have current values of current sources connected to respective emitters commonly connected in the three sets of differential pairs.

25. A linearized differential amplifier according to claim 23, wherein

ratio of the emitter areas of the transistors which make up the differential pairs of the three sets is 1:

7.872983, and 1;

1, and 7.872983;

1, respectively.