Silicon-on-insulator transistor with selectable body node to source node connection

• US 5,079,605 A
• Filed: 11/27/1989
• Issued: 01/07/1992
• Est. Priority Date: 07/29/1988
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Blake, Terence G. W.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): FAHMY, WAEL M
• Application Number:
  US07/441,591
• Time in Patent Office: 771 Days
• Field of Search: 357/23.7, 357/4, 357/86, 357/67 S, 357/23.9
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Abstract

A silicon-on-insulator MOS transistor (100) is disclosed which has contact regions on both the source (6) and drain (8) sides of the gate electrode (10) for (36,38) potentially making contact to the body node (12) from either side. Each contact region (36,38) is of the same conductivity type as the body node (12), (for example, a p-type region for an n-channel transistor), and may be formed by blocking all source/drain implants from the contact regions (36,38), so that the contact region (36,38) remains substantially with the same doping concentration as the of the body region (12). A mask is provided prior to silicidation so that the contact regions (36,38) on either side of the gate electrode (12) are not connected by silicide to the adjacent source/drain doped regions (6,8). Once a side is selected to be the source of the transistor, ohmic connection is then made between the abutting source region (6) and the contact region (36) by way of contacts (22,23) through an overlying interlevel dielectric (40) and metallization (25). A second embodiment of the transistor (200) is disclosed which provides such contact with reduction in the channel width, by allowing the lightly-doped drain extension of the source (19) and drain (18) to be present between the contact region (36,37,38) on both sides of its gate so that all of the contact regions on the mesa are connected through the body nodes of the transistors. A single body-to-source node connection can thus provide body node bais for all of the transistors on the mesa.

Claims

1. A transistor formed in a semiconductor layer overlying an insulating film, comprising:

a gate electrode overlying a body node portion of said semiconductor layer, said body node portion being of a first conductivity type and having first and second sides;

a drain region of said semiconductor layer, said drain region being of said second conductivity type and disposed adjacent a first side of said body node portion;

a source region of said semiconductor layer, said source region being of said second conductivity type, and disposed adjacent a second side of said body node portion;

a first contact region of said semiconductor layer, said first contact region being of said first conductivity type, disposed adjacent said source region and adjacent said second side of said body node portion;

a second contact region of said semiconductor layer, said second contact region being of said first conductivity type, disposed adjacent said drain region and adjacent said first side of said body node portion; and

an ohmic connection between said first contact region and said source region.

2. The transistor of claim 1, further comprising:

an interlevel dielectric overlying said source region; and

wherein said ohmic connection comprises a metal line connected to said first contact region and to said source region through contact vias in said interlevel dielectric.

3. The transistor of claim 1, wherein said drain, source and first contact regions extend through the full thickness of the semiconductor layer.

4. The transistor of claim 1, further comprising a gate dielectric layer disposed between said gate electrode and said body node portion.

5. The transistor of claim 1, further comprising:

sidewall dielectric filaments disposed along the sides of said gate electrode.

6. The transistor of claim 5, wherein said source region comprises:

a first portion adjacent said body node portion; and

a second portion adjacent said first portion and adjacent said first contact region, said second portion relatively heavily doped relative to said first portion.

7. The transistor of claim 6, wherein said first portion is disposed between said first contact region and said second side of said body node portion at the surface of said semiconductor layer, said first contact region being deeper than said first portion of said source region so that said first contact region is in contact with said body node portion at a location below said first portion of said source region.

8. The transistor of claim 1, wherein said source region comprises:

a clad portion having a refractory metal silicide film disposed thereover; and

an unclad portion, disposed between said clad portion and said first contact region, said unclad portion not having a refractory metal silicide film disposed thereover;

and wherein said drain region comprises;

a clad portion having a refractory metal silicide film disposed thereover; and

an unclad portion, disposed between said clad portion and said second contact region, said unclad portion not having a refractory metal silicide film disposed thereover.

9. The transistor of claim 8, further comprising:

an interlevel dielectric overlying said source region and said first contact region;

wherein said ohmic connection comprises a metal line connected to said first contact region and to said source region through contact vias in said interlevel dielectric;

and wherein the contact via in said interlevel dielectric in contact with said first contact region overlaps into said unclad portion of said source region.

10. The transistor of claim 8, further comprising:

an interlevel dielectric overlying said source region and said first contact region;

wherein said ohmic connection comprises a metal line connected to said first contact region and to said source region through contact vias in said interlevel dielectric;

and wherein the contact via in said interlevel dielectric in contact with said first contact region is fully disposed within said first contact region.

11. The transistor of claim 1, wherein said semiconductor layer is a mesa overlying said insulator layer.

12. The transistor of claim 11, wherein said first contact region is disposed adjacent a first edge of said mesa.

13. A transistor formed in a semiconductor layer overlying an insulating film, comprising:

a gate electrode overlying a body node portion of said semiconductor layer, said body node portion being of a first conductivity type and having first and second sides;

a drain region of said semiconductor layer, said drain region being of said second conductivity type and disposed adjacent a first side of said body node portion, said drain region comprising;

a clad portion having a refractory metal silicide film disposed thereover; and

an unclad portion, disposed between said clad portion and said second contact region, said unclad portion not having a refractory metal silicide film disposed thereover;

a source region of said semiconductor layer, said source region being of said second conductivity type, and disposed adjacent a second side of said body node portion, said source region comprising;

a clad portion having a refractory metal silicide film disposed thereover; and

an unclad portion, disposed between said clad portion and said first contact region, said unclad portion not having a refractory metal silicide film disposed thereover;

a first contact region of said semiconductor layer, said first contact region being of said first conductivity type, disposed adjacent said second side of said body node portion, said unclad portion of said source region being disposed between said first contact region and said clad portion of said source region; and

a second contact region of said semiconductor layer, said second contact region being of said first conductivity type, disposed adjacent said first side of said body node portion, said unclad portion of said drain region being disposed between said second contact region and said clad portion of said drain region.

14. The transistor of claim 13, further comprising ohmic connection between said first contact region and said source region.

15. The transistor of claim 13, further comprising:

an interlevel dielectric overlying said source region and said first contact region; and

a metal line in contact with said first contact region through a contact via in said interlevel dielectric.

16. The transistor of claim 15, wherein said metal line is also connected to said source region through a contact via in said interlevel dielectric;

and wherein the contact via in said interlevel dielectric in contact with said first contact region overlaps into said unclad portion of said source region.

17. The transistor of claim 15, wherein said metal line is also connected to said source region through a contact via in said interlevel dielectric;

and wherein the contact via in said interlevel dielectric in contact with said first contact region is fully disposed within said first contact region.

18. The transistor of claim 13, wherein each of said clad and unclad portions of said source region comprise:

a first portion adjacent said second side of said body node portion; and

a second portion adjacent said first portion and adjacent said first contact region, said second portion relatively heavily doped relative to said first portion.

19. The transistor of claim 18, wherein said first portion of said unclad portion of said source region is disposed between said first contact region and said second side of said body node portion at the surface of said semiconductor layer, said first contact region being deeper than said first unclad portion of said source region so that said fist contact region is in contact with said body node portion at a location below said first unclad portion of said source region.

20. An integrated circuit formed in a semiconductor layer overlying an insulating film, comprising:

first, second and third doped regions of a first conductivity type in said semiconductor layer, said first and second doped regions separated from one another by a first body region of a second conductivity type, and said second and third doped regions separated from one another by a second body region of said second conductivity type;

first and second gate electrodes overlying said first and second body regions, respectively;

first, second and third contact regions formed in said semiconductor layer adjacent said first, second and third doped regions, respectively, said first and second contact regions in ohmic contact with said first body region and said second and third contact regions in ohmic contact with said second body region; and

ohmic connection between one of said first, second and third contact regions and its adjacent first, second or third doped region.

21. The transistor of claim 20, further comprising:

an interlevel dielectric overlying said first, second and third doped regions and said first, second and third contact regions;

and wherein said ohmic connection comprises a metal line connected to said selected contact region and to its adjacent doped region through contact vias in said interlevel dielectric.

22. The transistor of claim 20, wherein said doped regions and said contact regions extend through the full thickness of the semiconductor layer.

23. The transistor of claim 20, further comprising a gate dielectric layer disposed between said gate electrodes and said body regions.

24. The transistor of claim 20, further comprising:

sidewall dielectric filaments disposed along the sides of said gate electrodes.

25. The transistor of claim 24, wherein said doped regions each comprise:

a first portion adjacent its adjacent body region; and

a second portion adjacent said first portion and adjacent its adjacent contact region, said second portion relatively heavily doped relative to said first portion.

26. The transistor of claim 20, wherein each doped region comprises:

a clad portion having a refractory metal silicide film disposed thereover; and

an unclad portion, disposed between said clad portion and its adjacent contact region, said unclad portion not having a refractory metal silicide film disposed thereover.

27. The transistor of claim 20, wherein said semiconductor layer is a mesa overlying said insulator layer.

28. The transistor of claim 27, wherein said first contact region is disposed adjacent a first edge of said mesa.