Method of making edge-connected integrated circuit structure

• US 5,081,063 A
• Filed: 07/20/1989
• Issued: 01/14/1992
• Est. Priority Date: 07/20/1989
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Vonno, Nicolaas V., Begley, Patrick A.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Dang, Trung
• Application Number:
  US07/382,388
• Time in Patent Office: 908 Days
• Field of Search: 437/180, 437/203, 437/204, 437/226, 437/906, 437/2, 437/4, 437/7, 437/188, 437/183
• US Class Current: 438/59
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49112 the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/1465 of the hybrid type
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A focal plane array and an associated technique for manufacturing such an array, employ a first, substantially planar semiconductor substrate, that contains a densely compacted array of photodiodes, interconnected with a plurality of second semiconductor substrates in which the signal processing electronics for the array are formed. The backside of the focal plane array-containing substrate has an associated array of conductive bumps to which the respective photodiodes on the imaging side are electrically connected. Within plural ones of second semiconductor substrates, each of which is associated with a respective row of the array of photodiodes there are integrated the signal processing electronics for that row. Formed along side edge portions of the second substrates are a plurality of metallic bumps which are conductively connected to the signal processing electronics. Each signal processing substrate is conductively joined to the photodiode chip by corresponding bumps that have been electroplated along the side edge portion of that second semiconductor substrate to internal conductive regions that terminate at that side edge portion. Each conductive region is preferably comprised of doped semiconductor material which extends to the side edge portion of the substrate and is connected to regions of the signal processing devices within the semiconductor substrate.

Claims

1. A method of forming a metallic link to a side portion of a semiconductor substrate comprising the steps of:

(a) forming, in said substrate, a region of doped semiconductor material capable of being electroplated with a metallic layer;

(b) attaching an electrode layer to a first portion of said region;

(c) removing material from said substrate, so as to define a said portion of said substrate at which a side portion of said regions spaced apart from said first portion thereof, is exposed; and

(d) electroplating a metallic layer onto said side portion of said region, using said electrode layer as an electroplating electrode, while placing said side portion of said region in contact with an electroplating solution.

2. A method according to claim 1, wherein step (a) comprises forming, in a first surface portion of said semiconductor substrate, a dielectric ally isolated pocket of semiconductor material containing said region of doped semiconductor material, and wherein step (b) comprises attaching said electrode layer to a top surface portion of said region.

3. A method according to claim 2, further including the step of:

(e) removing additional material from said substrate so as to define a side edge portion of said substrate which includes the side portion of said region to which a metallic layer has been electroplated in step (d).

4. A method of conductively connecting an array of photoresponsive devices that are supported within a first semiconductor substrate and for which respective conductive land portions are provided over a first surface of said first semiconductor substrate, to signal processing devices that are supported in a second semiconductor substrate comprising the steps of:

(a) forming, in said second semiconductor substrate, a plurality of regions of material capable of being plated with respective metallic layers and providing conductive connections between said regions and signal processing devices that are supported within said second semiconductor substrate;

(b) removing material from said second semiconductor substrate, so as to form a side edge portion of said second semiconductor substrate exposing respective side portions of said regions;

(c) plating respective metallic layers to the respective side portions of said regions and thereby providing a plurality of metallic land portions at a side edge portion of said second semiconductor substrate that are conductively connected to said plurality of signal processing devices supported therein; and

(d) bringing said side edge portion of said second semiconductor substrate into adjacent alignment with plural conductive land portions of said first semiconductor substrate and conductively joining said plural conductive land portions of said first semiconductor substrate with plural metallic layers that have been plated to side portions of said regions in step (c).

5. A method according to claim 4, wherein step (c) further includes removing additional material from said second semiconductor substrate, so as to define a side edge of said second semiconductor substrate which includes the side portions of said regions to which metallic layers have been plated in step (c).

6. A method according to claim 4, wherein step (a) comprises the steps of:

(a1) forming, in a first surface portion of said second semiconductor substrate, a plurality of pockets, each of which contains a respective region of doped semiconductor material, and

(a2) attaching plural conductive layers to top surface portions of respective ones of said regions.

7. A method according to claim 6, wherein step (b) comprises removing material from said pockets so as to expose side portions of said regions, spaced apart from said conductive layers, and wherein step (c) comprises electroplating metallic layers onto exposed side portions of said regions, using said conductive layers as electroplating electrodes, while placing the exposed side portions of said regions in contact with an electroplating solution.

8. A method according to claim 4, wherein said array comprises a two-dimensional array of photoresponsive devices and step (d) comprises bringing the side edge portions of a plurality of adjacent second semiconductor substrates, that have been formed in accordance with step (c), into alignment with respective sets of plural conductive land portions of said first semiconductor substrate and conductively joining the plural conductive land portions of respective ones of said sets with plural metallic layers that have been plated to side portions of regions o respective ones of said second semiconductor substrates.

9. A method of manufacturing an opto-electronic imaging system comprising the steps of:

(a) providing a first semiconductor substrate having formed in a first surface thereof a matrix of rows and columns of photoresponsive devices and having extending from a second surface thereof an associated matrix of conductive land portions that are electrically coupled with respective ones of said photoresponsive devices;

(b) providing, for each row of said matrix of photoresponsive devices, a respective second semiconductor substrate into which are integrated semiconductor regions interconnected to form signal processing devices for processing the outputs of an associated row of said matrix of photoresponsive devices;

(c) forming, along a side edge portion of each respective second semiconductor substrate, a plurality of metallic bumps which are conductively connected to signal processing devices within said second semiconductor substrate; and

(d) bringing the side edge portion of a respective second semiconductor substrate into adjacent alignment with plural conductive land portions of said first semiconductor substrate and conductively joining said plural conductive land portions of said first semiconductor substrate with plural metallic bumps along side portions of said respective second semiconductor substrate.

10. A method according to claim 9, wherein step (c) comprises

(c1) forming, in each respective second semiconductor substrate, a plurality of regions of material capable of being plated with respective metallic layers and providing conductive connections between said regions and signal processing devices within said second semiconductor substrate;

(c2) removing material from each second semiconductor substrate, so as to form a side edge portion of each second semiconductor substrate exposing respective side portions of said regions; and

(c3) plating respective metallic bumps to the respective side portions of said regions and thereby providing a plurality of metallic bumps at a side edge portion of each second semiconductor substrate that are conductively connected to signal processing devices therein.

11. A method of forming an edge connector to a substrate comprising the steps of:

(a) forming, in said substrate, a doped semiconductor region capable of being bonded with conductive material;

(b) removing material of said doped semiconductor region and exposing a side portion o said doped semiconductor region; and

(c) bonding conductive material to said exposed side portion of said ad doped semiconductor region, and wherein

step (a) comprises the steps of;

(a1) forming, in a first surface portion of a semiconductor substrate, a pocket containing a region of doped semiconductor material, and

(a2) attaching a conductive layer to a top surface portion of said region, and wherein

step (b) comprises removing material from said pocket, so as to expose a side portion of said region, spaced apart from said conductive layer, and wherein

step (c) comprises electroplating a metallic layer onto said exposed side portion of said region, using said conductive layer as an electroplating electrode, while placing said exposed side portion of said region in contact with an electroplating solution.

12. A method according to claim 11, wherein step (a2) includes the steps o selectively forming a dielectric layer over the surface of said substrate so a s to expose a top surface portion of said region, and forming said conductive layer on said dielectric layer so s to extend through an aperture therein and contact said region.

13. A method of forming an edge connector to a substrate comprising the steps of:

(a) forming, in said substrate, a region of material capable o being bonded with conductive material and extending laterally within said substrate so as to intersect the eventual edge of said substrate;

(b) removing material of said substrate so as to expose a side portion of said region at said eventual edge of said substrate; and

(c) bonding conductive material to said exposed side portion of said region, and wherein

step (a) comprises the steps of;

(a1) forming, in a first surface portion of a semiconductor substrate, a pocket containing a region of doped semiconductor material extending laterally within said substrate so as to intersect the eventual edge of said substrate, and

(a2) attaching a conductive layer to a top surface portion of said region, and wherein

step (b) comprises removing material from said pocket, so as to expose a side portion of said region, spaced apart from said conductive layer, and wherein

step (c) comprises electroplating a metallic layer onto said exposed side portion of said region, using said conductive layer as an electroplating electrode, while placing said exposed side portion of said region in contact with an electroplating solution.

14. A method according to claim 13, wherein step (a2) includes the steps of selectively forming a dielectric layer over the surface of said substrate so as to expose a top surface potion of said region, and forming said conductive layer on said dielectric layer so as to extend through an overture therein and contact said region.