Chip mounting substrate having an integral molded projection and conductive pattern

• US 5,081,520 A
• Filed: 05/16/1990
• Issued: 01/14/1992
• Est. Priority Date: 05/16/1989
• Status: Expired due to Fees

• Current Assignee: Minolta Camera Kabushiki Kaisha
• Original Assignee: Minolta Camera Kabushiki Kaisha
• Inventors: Yoshii, Masayuki, Kowa, Mika, Mizumo, Yoshiyuki, Oku, Shunji
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US07/525,082
• Time in Patent Office: 608 Days
• Field of Search: 357/67, 357/74, 357/72, 357/80, 357/68, 357/76, 174/260, 174/261, 174/263, 174/255, 361/404, 361/406
• US Class Current: 257/702
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/10165 Alignment aids
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73103 Bump and layer connectors
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81365 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81903 by means of a layer connector
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/09045 : Locally raised area or protrusion of insulating substrate rigid curved substrate H05K2201/09018
• CPC Class Codes: H05K 2201/09118 : Moulded substrate
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457

Abstract

The present invention provides an improved chip mounting method for mounting an IC chip on a substrate, comprising the steps of; integrally molding a projection on the substrate, the projection being located on a surface of the substrate on which the IC chip will be mounted; forming a conductive pattern on the projection and on a necessary portion of the substrate; forming a connecting layer on the conductive pattern formed on the projection; and fixing said IC chip on the substrate while electrically connecting an exposed electrode of the IC chip with the conductive pattern formed on the projection through the connecting layer.

Claims

1. A chip mounted substrate on which an IC chip, having an exposed electrode, is mounted, comprising:

a substrate formed of an insulating material and integrally molded with a projection on a surface thereof;

a conductive pattern formed on the projection and on a necessary portion of the substrate;

a connecting layer formed on the conductive pattern formed on the projection; and

an IC chip fixed on the substrate while electrically connecting the exposed electrode with said conductive pattern formed on the projection through said connecting layer.

2. A chip mounted substrate as claimed in claim 1, further comprising an adhesive provided for sealing said IC chip on the substrate.

3. A chip mounted substrate as claimed in claim 1, wherein said substrate is formed as an IC card.

4. A chip mounted substrate as claimed in claim 2, wherein said adhesive is made of a hot-melt type so that said IC chip can be removed from the substrate after said IC chip has been once mounted on the substrate.

5. A chip mounted substrate as claimed in claim 2, wherein said substrate is made of a transparent material and said adhesive is made of an ultraviolet-ray-setting adhesive.

6. A chip mounted substrate as claimed in claim 1, wherein said substrate is made of a transparent material and is formed as a part of a liquid crystal device.

7. A chip mounted substrate as claimed in claim 1, further comprising a sealing member for sealing said IC chip on the substrate.

8. A chip mounted substrate as claimed in claim 1, wherein said IC chip is composed of an optical element which requires incident or emission of light.

9. A chip mounted substrate as claimed in claim 8, wherein said optical element is selected from a group including a silicon photo cell (SPC), a light emitting diode (LED) , and an electrically programable read only memory (EPROM).

10. A chip mounted substrate as claimed in claim 5, wherein said connecting layer is made of solder.

11. A chip mounted substrate as claimed in claim 5, wherein said connecting layer is made by plating tin upon the conductive pattern positioned on the projection.

12. A chip mounted substrate as claimed in claim 5, wherein said connecting layer is made by plating gold upon the conductive pattern positioned on the projection.

13. A chip mounted substrate as claimed in claim 5, wherein said connecting layer is made of gold paste.

14. A chip mounted substrate as claimed in claim 5, wherein said connecting layer is made is adhesive is electrically conductive.

15. A chip mounted substrate as claimed in claim 5, further comprising adhesive tape of electrically anisotropic conductive provided on said conductive pattern and positioned on the projection.

16. A chip mounted substrate as claimed in claim 5, further comprising a frame integrally formed on the substrate with the projection, said frame being used for positioning said IC chip on the substrate.

17. A chip mounted substrate as claimed in claim 5, wherein said substrate is formed as an outside member of an electrical device.

18. A chip mounted substrate on which an IC chip, having an exposed electrode, is mounted, comprising:

a substrate formed of an insulating material and integrally molded with a pair of spaced projections on a surface thereof;

a conductive pattern formed on the projections and on a necessary portion of the substrate;

a connecting layer formed on the conductive pattern formed on the projections;

an IC chip having a pair of exposed electrodes fixed on the substrate while electrically connecting the exposed electrodes with said conductive patterns formed on the projections through said connecting layer, the projections being of a sufficient height above said substrate surface to support said IC chip with a gap between said IC chip and said substrate surface, and

means extending between said projections and said gap to secure the IC chip to said substrate.