Enclosed ferroelectric stacked capacitor

• US 5,081,559 A
• Filed: 02/28/1991
• Issued: 01/14/1992
• Est. Priority Date: 02/28/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Fazan, Pierre, Liu, Yauh-Ching, Chan, Hiang C.
• Primary Examiner(s): Griffin, Donald
• Application Number:
  US07/662,671
• Time in Patent Office: 320 Days
• Field of Search: 361/311-313, 357/23.6, 365/149, 437/30, 437/41, 437/52, 437/60
• US Class Current: 361/313
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

This invention relates to semiconductor circuit memory storage devices and more particularly to a process to develop three-dimensional stacked cell capacitors using a PZT ferroelectric material as a storage cell dielectric for use in high-density dynamic random access memory (DRAM) arrays. The present invention employs using PZT ferroelectric for the storage cell dielectric in three-dimensional stacked capacitor technology and develops an existing stacked capacitor fabrication process to construct a PZT three-dimensional stacked capacitor cell (the EFSC) that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions. A capacitance gain of 3 to 10X or more over that of a conventional 3-dimensional storage cell is gained by using PZT ferroelectric as the storage cell dielectric.

Claims

1. A storage capacitor constructed on a silicon substrate, said capacitor comprising:

a conductive storage node plate comprising a rectangular upper portion and a lower portion that extends downward and makes contact at a storage node junction, said storage node plate conforms to an existing topology of said silicon substrate;

a cell dielectric adjacent and coextensive said storage node plate except at said storage node junction contact; and

conductive double cell plates adjacent and coextensive said cell dielectric.

2. A DRAM storage capacitor constructed on a silicon substrate, said capacitor comprising:

a first conductive layer, said first conductive layer patterned to form a storage node plate having an upper rectangular shaped portion and a lower portion that extends downward and makes contact at a storage node junction, said storage node plate conforms to an existing topology of said silicon substrate;

a second conductive layer, said second conductive layer patterned to form a rectangular shaped bottom cell plate of a double cell plate;

a cell dielectric layer being adjacent said storage node plate and said bottom cell plate and coextensive therewith except at a region for said contact at said storage node junction; and

a third conductive layer forming a top cell plate of said double cell plate, said top plate connecting to said bottom cell plate to form a double cell plate, said double cell plate being adjacent said second cell dielectric layer and coextensive therewith.

3. The capacitor of claim 2, wherein said first, said second and said third conductive layers are selected from the group consisting essentially of tungsten or tungsten silicide.

4. A DRAM memory array constructed on a silicon substrate, said memory array comprising:

a plurality of active areas arranged in parallel interdigitated rows and parallel non-interdigitated columns, said active areas separated by isolation means, each of said active areas having a digit line junction, and a storage node junction;

a plurality of parallel conductive word lines aligned along said rows such that a digit line junction and a storage node junction within each active area are bridged by a word line, each word line being insulated from associated active areas by a gate dielectric layer;

a plurality of parallel conductive digit lines, aligned along said columns such that a digit line makes electrical contact with each digit line junction within a column, said digit lines running perpendicular to and over said word lines forming a 3-dimensional, waveform-like topology, said digit and word lines electrically separated from one another by isolation means; and

at least one storage capacitor for each active area, each capacitor having a storage node plate that is in electrical contact with its associated active area and a double cell plate that is common to the entire array, each storage node plate being insulated from said double cell plate by a cell dielectric layer.

5. The memory array of claim 4, wherein said capacitor comprises:

a first conductive layer, said first conductive layer patterned to form a storage node plate having an upper rectangular shaped portion and a lower portion that extends downward and makes contact at a storage node junction, said storage node plate conforms to an existing topology of said silicon substrate;

a second conductive layer, said second conductive layer patterned to form a rectangular shaped bottom cell plate of a double cell plate;

a cell dielectric layer being adjacent said storage node plate and said bottom cell plate and coextensive therewith except at a region for said contact at said storage node junction; and

a third conductive layer forming a top cell plate of said double cell plate, said top plate connecting to said bottom cell plate to form a double cell plate, said double cell plate being adjacent said second cell dielectric layer and coextensive therewith.

6. The capacitor of claim 4, wherein said first, said second and said third conductive layers are selected from the group consisting essentially of tungsten or tungsten silicide.

7. A process for fabricating a DRAM array on a silicon substrate, said process comprising the following sequence of steps:

creating a plurality of separately isolated active areas arranged in parallel interdigitated rows and parallel non-interdigitated columns;

creating a gate dielectric layer on top of each active area;

depositing a first conductive layer superjacent surface of said array;

depositing a first dielectric layer superjacent said first conductive layer;

masking and etching said first conductive and said first dielectric layers to form a plurality of parallel conductive word lines aligned along said rows such that each said word line passes over a inner portion of each said active area being separated therefrom by a remanent of said gate dielectric layer;

creating of a conductively-doped digit line junction and storage node junction within each said active area on opposite sides of each said word line;

depositing a second dielectric layer superjacent said array surface;

creating a first aligned buried contact location at each said digit line junction in each said active area;

depositing a second conductive layer superjacent said array surface, said second conductive layer making direct contact to said digit line junctions at said first buried contact locations;

depositing a third dielectric layer superjacent to said second conductive layer;

masking and etching said second conductive layer and said third dielectric layer to form a plurality of parallel conductive digit lines aligned along said columns such that a digit line makes electrical contact at each digit line junction within a column, said digit lines running perpendicular to and over said word lines forming a 3-dimensional, waveform-like topology;

depositing a fourth dielectric layer on surface of said silicon;

masking and etching a buried contact location allowing access to an active area and thereby forming vertical sidewalls within opening of said buried contact location;

depositing a third conductive layer superjacent said fourth dielectric layer and said buried contact opening;

planarizing said third conductive layer;

patterning said third conductive layer to form an upper rectangular shaped portion and a lower portion of a storage node, said lower portion making contact to said active area at said buried contact location, said third conductive layer conforming to said 3-dimensional, waveform shaped topology;

depositing a fifth dielectric layer superjacent said existing waveform shaped topology;

anisotropically etching said fifth dielectric layer thereby forming vertical dielectric spacers adjacent sidewalls of said conductive upper rectangular shaped portion;

depositing and planarizing a fourth conductive layer superjacent said existing waveform shaped topology;

isotropically etching said vertical dielectric spacers thereby leaving a conductive rectangular shaped bottom cell plate;

depositing a cell dielectric layer superjacent said existing waveform shaped topology, thereby enclosing exposed portion of said bottom cell plate and upper portion of said storage node plate;

depositing a fifth conductive layer superjacent said cell dielectric layer, thereby forming a top cell plate, said top cell plate connecting to said bottom cell plate, said top and said bottom cell plates combining to form a double cell plate common to the entire memory array.

8. A process as recited in claim 7, wherein said gate dielectric layer is oxide.

9. A process as recited in claim 7, wherein said first and said second conductive layers comprise a layer of tungsten silicide and a layer of conductively-doped polysilicon.

10. A process as recited in claim 7, wherein said first and said second dielectric layers are selected from the group consisting essentially of oxide or nitride.

11. A process as recited in claim 7, wherein said third dielectric layer is selected from the group consisting essentially of oxide or nitride.

12. A process as recited in claim 7, wherein said third, said fourth and said fifth conductive layers are selected from the group consisting essentially of tungsten or tungsten silicide.

13. A process as recited in claim 7, wherein said second, said third dielectric layers and said cell dielectric layers are deposited by chemical vapor deposition.

14. A process as recited in claim 7, wherein said third dielectric layer is selected from the group consisting essentially of oxide, nitride or polyimide.

15. A process as recited in claim 7, wherein said isotropically etching said vertical dielectric spacers is a time controlled etch.

16. A process as recited in claim 7, wherein said cell dielectric layer is a PZT ferroelectric material.

17. A process as recited in claim 16, wherein said PZT ferroelectric material is applied by a sol-gel method.

18. A process for fabricating a DRAM storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the following sequence of steps:

depositing a first dielectric layer on surface of said silicon;

masking and etching a buried contact location allowing access to an active area and thereby forming vertical sidewalls within opening of said buried contact location;

depositing a first conductive layer superjacent said first dielectric layer and said buried contact opening;

planarizing said first conductive layer;

patterning said first conductive layer to form an upper rectangular shaped portion and a lower portion of a storage node, said lower portion making contact to said active area at said buried contact location, said first conductive layer conforming to said 3-dimensional, waveform shaped topology;

depositing a second dielectric layer superjacent said existing waveform shaped topology;

anisotropically etching said second dielectric layer thereby forming vertical dielectric spacers adjacent sidewalls of said conductive upper rectangular shaped portion;

depositing and planarizing a second conductive layer superjacent said existing waveform shaped topology;

isotropically etching said vertical dielectric spacers thereby leaving a conductive rectangular shaped bottom cell plate;

depositing a cell dielectric layer superjacent said existing waveform shaped topology, thereby enclosing exposed portion of said bottom cell plate and upper portion of said storage node plate;

depositing a third conductive layer superjacent said cell dielectric layer, thereby forming a top cell plate, said top cell plate connecting to said bottom cell plate, said top and said bottom cell plates combining to form a double cell plate common to the entire memory array.

19. A process as recited in claim 18, wherein said first dielectric layer is selected from the group consisting essentially of oxide or nitride.

20. A process as recited in claim 18, wherein said first, said second and said third conductive layers are selected from the group consisting essentially of tungsten or tungsten silicide.

21. A process as recited in claim 18, wherein said first, said second dielectric layers and said cell dielectric layers are deposited by chemical vapor deposition.

22. A process as recited in claim 18, wherein said first dielectric layer is selected from the group consisting essentially of oxide, nitride or polyimide.

23. A process as recited in claim 18, wherein said isotropically etching said vertical dielectric spacers is a time controlled etch.

24. A process as recited in claim 18, wherein said cell dielectric layer is a PZT ferroelectric material.

25. A process as recited in claim 24, wherein said PZT ferroelectric material is applied by a sol-gel method.