Multiprocessor controller having time shared control store

• US 5,081,609 A
• Filed: 01/10/1989
• Issued: 01/14/1992
• Est. Priority Date: 01/10/1989
• Status: Expired due to Term

• Current Assignee: Honeywell Bull Incorporated (Atos SE)
• Original Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Inventors: Gardner, Joseph P., Votolato, Alfred F., Getson, Edward F. Jr., Bradley, John W.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Coleman, Eric
• Application Number:
  US07/295,629
• Time in Patent Office: 1,099 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/58
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Abstract

A controller connected between a system bus and peripheral devices has at least two microprocessors. One controls the data transfers with the peripheral devices, and the other controls data transfers with the system bus. The microprocessors share a data buffer and control store. This sharing is possible because of the controller timing means which synchronizes exclusive access to the shared components of the controller. When first initialized, the microprocessors are directed to execute a test instruction which points them to the beginning of their set of microinstructions. Once pointed to their set of microinstructions, normal operation may begin.

Claims

1. A controller for controlling data transfers between a data processing system bus and peripheral devices, comprising:

a. at least one data buffer for temporarily storing data as it passes between the data processing system bus and the peripheral devices;

b. a first microprocessor for controlling data transfers between the data processing system bus and the at least one data buffer;

c. a second microprocessor in communication with the first microprocessor for controlling data transfers between the data buffer and the peripheral devices;

d. a control store connected to both microprocessors for storing microinstructions that control operation of the respective microprocessors; and

e. a timing means which produces a clock signal divided into cycles wherein each microprocessor is assigned a portion of a cycle during which it may exclusively access the control store.

2. A controller as recited in claim 1 further comprising a scratch pad memory connected to both microprocessors.

3. A controller as recited in claim 2 wherein each microprocessor is assigned a portion of a cycle in which it may exclusively access the scratch pad memory or exclusively seize the data buffer.

4. A controller as recited in claim 1 wherein the dual port control store comprises a random access memory.

5. A controller as recited in claim 1 wherein there are two data buffers.

6. A controller as reoited in claim 1 wherein the control store is loaded with separate sets of microinstructions for each microprocessor.

7. A controller as recited in claim 1 wherein the control store is prepared for operation by loading it with a test instruction which directs each microprocessor to the beginning of its respective set of microinstructions.

8. A controller as reoited in claim 7 wherein the test instruction is a conditional branch instruction.

9. A peripheral device controller for controlling data transfers between a data processing system bus and peripheral devices, comprising:

a. at least one data buffer for temporarily storing data as it passes between the data processing system bus and the peripheral devices;

b. a first microprocessor for controlling data transfers between a data processing system bus and peripheral devices, comprising;

a. at least one data buffer for temporarily storing data as it passes between the data processing system bus and the peripheral devices;

b. a first microprocessor for controlling data transfers between the at least one data buffer and the data processing system bus;

c. a second microprocessor for controlling data transfers between the at least one data buffer and the peripheral devices;

d. a control store comprising a random access memory for storing sets of microinstructions for each microprocessor wherein the control store is prepared for operation by loading it with a test instruction which directs each of the microprocessors to the beginning of its respective set of microinstructions; and

e. a timing means which generates a clock signal which is divided into cycles wherein each microprocessor is assigned a portion of a cycle during which it may exclusively access the control store.

10. A controller for efficiently transferring information between peripheral devices and a system bus comprising

a. a first synchronously operated processor for receiving and processing input/output commands from said system by specifying operation to be performed by said bus;

b. a second synchronously operated processor for transferring information to the peripheral devices;

c. a control store coupled to said first and second processor comprising a first and a second set of storage locations for storing sets of a corresponding number of microinstructions for each said processor wherein said microinstructions define operations to be performed by said processors;

d. a timing means for application to said first and second processors for synchronizing their operations relative to each other in a predetermined manner, each sequence having at least first and second intervals for defining the time period that said first and second processors respectively have exclusive access to said control store; and

e. at least one data buffer for temporarily storing data as it passes between the data processing system bus and the peripheral devices.

11. A method of synchronizing elements of a controller having a buffer, first and second microprocessors, a timing means and a control store which controls data transfers between a data processing system bus and peripheral devices, comprising:

(a) dividing time into cycles using the timing means;

(b) at the start of a first portion of a cycle, performing an instruction fetch by the first microprocessor from the control store;

(c) during said first portion of said cycle,

beginning execution by the first microprocessor of the microinstruction fetched by he first microprocessor; and

completing execution by the second microprocessor of a microinstruction previously fetched by the second microprocessor;

(d) at the start of a second portion of said cycle, performing an instruction fetch by the second microprocessor from the control store;

(e) during said second portion of said cycle, p1 beginning execution by the second microprocessor of the microinstruction fetched by the second microprocessor; and

(f) repeating the above steps b through e.

12. A method of synchronizing elements of a controller as recited in claim 11 wherein execution of the microprocessor may comprise exclusively accessing a scratch pad memory or exclusively seizing a data buffer.

13. A method of synchronizing elements of a controller as recited in claim 11 wherein each said microprocessor may only exclusively access the scratch pad memory or exclusively seize a data buffer during an assigned one of said portions of cycles which is not assigned to other said microprocessors, and the assigned one of said portions is the same for each cycle.

14. A method of preparing a control store of a controller having a data buffer, first and second microprocessors, and a timing means for operation comprising:

(a) loading a test instruction into the control store;

(b) loading a set of microinstructions for each microprocessor into the control store;

(c) dividing time into cycles using the timing means;

(d) at the start of a first portion of a cycle, fetching the test instruction from the control store by the first microprocessor;

(e) during said first portion of said cycle, beginning execution of the test instruction by the first microprocessor;

(f) at the start of a second portion of said cycle, fetching the test instruction by the second microprocessor;

(g) during said second portion of said cycle,

completing execution of the test instruction by the first microprocessor wherein execution of the test instruction comprises directing the first microprocessor to a first microinstruction in its set of microinstructions;

beginning execution of the test instruction by the second microprocessor;

(h) at the start of a first portion of a next cycle, fetching the first microinstruction at the beginning of the set of microinstructions for the first microprocessor by he first microprocessor;

(i) during said first portion of said next cycle, completing execution of the test instruction by the second microprocessor comprises directing the second microprocessor of a first microinstruction in its set of microinstructions;

(j) fetching the first microinstruction in the set of microinstructions for the second microprocessor by the second microprocessor.