Use of polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers

• US 5,082,796 A
• Filed: 07/24/1990
• Issued: 01/21/1992
• Est. Priority Date: 07/24/1990
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Razouk, Reda R., El-Diwany, Monir H., Brassington, Michael P.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US07/557,264
• Time in Patent Office: 546 Days
• Field of Search: 437/44, 437/191, 437/162, 437/56, 437/35, 437/34, 437/59, 148/DIG. 19
• US Class Current: 438/202
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of constructing a semiconductor structure wherein the polysilicon gate layer in a CMOS or BiCMOS structure incorporating LDD structures may be used for local interconnect. In one embodiment of the invention directed to a BiCMOS process, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide then is thermally grown on the silicon substrate. A thin layer of polysilicon is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing, and then both the thin polysilicon layer and the gate oxide layer are etched from the bipolar and MOS regions where the respective emitter and gates are to be formed and where buried contacts are to be made. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for defining the bipolar emitter, the MOS gates, and the local interconnects. A conformal silicon dioxide layer is subsequently deposited and etched for forming oxide spacers on the sidewalls of the polysilicon layer. By selectively doping the polysilicon layer and exposed portions of the substrate, a continuous active region is formed beneath the polysilicon layer and the sidewall spacers.

Claims

1. A method of constructing portions of a metal oxide semiconductor structure comprising the steps of, in sequence,:

depositing a polysilicon layer contacting a semiconductor substrate;

implanting the polysilicon layer with a first conductivity type impurity;

etching the polysilicon layer for forming a buried contact to the substrate with the polysilicon layer and for exposing portions of the substrate adjacent to the buried contact;

lightly doping exposed portions of the substrate adjacent to the buried contact by implanting the substrate with the first conductivity type impurity;

forming a nonconductive oxide spacer on a sidewall of the polysilicon layer and contacting the substrate;

heavily doping the substrate for later forming one of a source or drain region by implanting the substrate with the first conductivity type impurity adjacent to the oxide spacer; and

heating the substrate for forming the source or drain region adjacent to the oxide spacer and for forming a continuous first conductivity type region directly beneath the polysilicon layer and the oxide spacer, the continuous first conductivity type region contacting the formed source or drain region.

2. The method according to claim 1 further comprising the steps of:

prior to the substrate implanting step performed prior to the oxide spacer forming step, etching the substrate so that a portion of the substrate adjacent the buried contact is lower than a portion of the substrate beneath the buried contact and defines a generally vertical substrate wall; and

wherein the heating step further comprises the step of heating the substrate so that a continuous first conductivity-type region is formed beneath the polysilicon layer, along the substrate wall, and beneath the oxide spacer.

3. The method according to claim 2 wherein the heating step further comprises the step of heating the substrate so that the portion of the first conductivity-type region beneath the polysilicon layer is formed by out diffusion of the first conductivity-type impurity from the polysilicon layer.

4. The method according to claim 3 wherein the heating step further comprises the step of heating the substrate so that the portion of the first conductivity-type region along the substrate wall is formed by diffusion of the first conductivity-type impurity implanted in the substrate prior to the oxide spacer forming step.

5. The method according to claim 4 wherein the substrate implanting step prior to the oxide spacer forming step further comprises the step of tilting the substrate for increasing the amount of first conductivity-type impurity implanted in the substrate wall.

6. The method according to claim 5 wherein the polysilicon layer depositing step further comprises the step of depositing the polysilicon layer to a thickness of from approximately 2000 Å

to approximately 4000 Å

.

7. The method according to claim 6 wherein the oxide spacer forming step further comprises the steps of:

depositing a conformal silicon dioxide layer to a thickness of from approximately 1500 Å

to approximately 4000 Å

; and

anisotropically etching the conformal silicon dioxide layer for forming the oxide spacer.

8. The method according to claim 7 wherein the heating step further comprises the step of heating the semiconductor structure at a temperature of approximately 900°

C. for approximately 30 to 40 minutes.

9. The method according to claim 8 wherein the conformal silicon dioxide layer depositing step further comprises the step of depositing the conformal silicon dioxide layer to a thickness of approximately 2000 Å

.

34. The method according to claim 1 wherein the polysilicon layer implanting step comprises the step of implanting the polysilicon layer with the first conductivity type impurity to a concentration of from approximately 1×

10¹⁵ to approximately 1×

10¹⁶ atoms/cm².

35. The method according to claim 1 wherein the substrate implanting step performed prior to the oxide spacer forming step comprises the step of implanting the substrate with the first conductivity type impurity to a concentration of approximately 1×

10¹³ to approximately 1×

10¹⁴ atoms/cm².

36. The method according to claim 1 wherein the substrate implanting step performed after the oxide spacer forming step comprises the step of implanting the substrate with the first conductivity type impurity to a concentration of approximately 5×

10¹⁵ atoms/cm².

37. The method according to claim 1 wherein the polysilicon layer implanting step comprises the step of implanting the polysilicon layer with arsenic to a concentration of approximately 1×

10¹⁵ to approximately 1×

10¹⁶ atoms/cm², wherein the substrate implanting step performed prior to the oxide spacer forming step comprises the step of implanting the substrate with phosphorous to a concentration of approximately 1×

10¹³ to 1×

10¹⁴ atoms/cm², and wherein the substrate implanting step performed after the oxide spacer forming step comprises the step of implanting the substrate with arsenic to a concentration of approximately 5×

10¹⁵ atoms/cm².

38. The method according to claim 1 wherein the step of implanting the substrate performed after the oxide spacer forming step comprises the step of implanting the substrate with the first conductivity type impurity for forming one of a source region or a drain region of the semiconductor structure.

10. A method of constructing a semiconductor structure comprising the steps of:

forming a bipolar region in a silicon substrate for a bipolar device, the bipolar region having a first region, termed a collector region, and a second region, the first and second regions being separated by a first field oxide region;

forming a MOS region in the silicon substrate for a MOS device, the MOS region being separated from the bipolar region by a second field oxide region;

growing a thin oxide layer on the bipolar region and on the MOS region;

depositing a thin polysilicon layer over the thin oxide layer in the bipolar region and in the MOS region;

removing the thin polysilicon layer and the thin oxide layer from the second region and from regions of the substrate where first and second buried contacts to the substrate are to be made;

depositing a thick polysilicon layer on the bipolar region and on the MOS region;

masking a portion of the thick polysilicon layer in the second region for defining an emitter;

masking a portion of the thick polysilicon layer in the MOS region for defining a gate;

masking portions of the thick polysilicon layer for defining the first and second interconnected buried contacts to the substrate;

etching the polysilicon in the bipolar and MOS regions for forming an emitter of a bipolar device, a gate of an MOS device, and first and second interconnected polysilicon buried contacts to the substrate;

doping the portion of the polysilicon forming the first buried contact with a first impurity;

doping the portion of the substrate adjacent to the first buried contact with the first impurity;

doping the portion of the polysilicon forming the second buried contact with a second impurity;

doping the portion of the substrate adjacent to the second buried contact with the second impurity;

forming a first oxide spacer on a sidewall of the portion of the polysilicon forming the first buried contact;

forming a second oxide spacer on a sidewall of the portion of the polysilicon forming the second buried contact; and

heating the substrate so that a continuous first impurity-doped region is formed beneath the first buried contact and the first oxide spacer, and so that a continuous second impurity doped region is formed beneath the second buried contact and the second oxide spacer.

11. The method according to claim 10 wherein the first and second impurities have the same conductivity type.

12. The method according to claim 10 wherein the first and second impurities have different conductivity types.

13. The method according to claim 10 wherein the step of doping the portion of the substrate adjacent to the first buried contact is performed after the first oxide spacer forming step.

14. The method according to claim 13 further comprising the steps of:

prior to the first spacer forming step, etching the portion of the substrate adjacent to the first buried contact to a level below the portion of the substrate beneath the first buried contact for defining a first generally vertical substrate wall;

thereafter, and prior to the first spacer forming step, implanting the substrate with the first impurity; and

wherein the substrate heating step further comprises the step of heating the substrate so that a continuous first impurity-doped region is formed beneath the first buried contact, adjacent the first substrate wall, and beneath the first oxide spacer.

15. The method according to claim 14 wherein the heating step further comprises the step of heating the substrate so that the portion of the first impurity-doped region beneath the buried contact is formed by out-diffusion of the first impurity from the thick polysilicon layer.

16. The method according to claim 15 wherein the heating step further comprises the step of heating the substrate so that the portion of the first impurity-doped region adjacent the substrate wall is formed by diffusion of the first impurity implanted in the substrate prior to the first spacer forming step.

17. The method according to claim 16 wherein the substrate implanting step performed prior to the first spacer forming step further comprises the step of tilting the substrate for increasing the amount of first impurity implanted in the first substrate wall.

18. A method of constructing a semiconductor structure comprising the steps of:

forming a first MOS region in a silicon substrate for a first channel type MOS device;

forming a second MOS region in the silicon substrate for a second channel type MOS device, the second MOS region being separated from the first MOS region by a field oxide region;

growing a thin oxide layer on the first and second MOS regions;

depositing a thin polysilicon layer over the thin oxide layer in the first and second MOS regions;

removing the thin polysilicon layer and the thin oxide layer from regions of the substrate where first and second buried contacts to the substrate are to be made;

depositing a thick polysilicon layer on the first and second MOS regions;

masking a portion of the thick polysilicon layer in the first MOS region for defining a first gate;

masking a portion of the thick polysilicon layer in the second MOS region for defining a second gate;

masking portions of the thick polysilicon layer for defining first and second interconnected buried contacts to the substrate;

etching the polysilicon in the first and second MOS regions for forming corresponding first and second gates for the first and second MOS devices, and first and second interconnected polysilicon buried contacts to the substrate;

doping the portion of the polysilicon forming the first buried contact with a first impurity;

doping the portion of the substrate adjacent to the first buried contact with the first impurity;

doping the portion of the polysilicon forming the second buried contact with a second impurity;

doping the portion of the substrate adjacent to the second buried contact with the second impurity;

forming a first oxide spacer on a sidewall of the portion of the polysilicon forming the first buried contact;

forming a second oxide spacer on a sidewall of the portion of the polysilicon forming the second buried contact; and

heating the substrate so that a continuous first impurity-doped region is formed beneath the first buried contact and the first oxide spacer, and so that a continuous second impurity doped region is formed beneath the second buried contact and the second oxide spacer.

19. The method according to claim 18 wherein the first and second impurities have the same conductivity type.

20. The method according to claim 18 wherein the first and second impurities have different conductivity types.

21. The method according to claim 18 wherein the step of doping the portion of the substrate adjacent to the first buried contact is performed after the first oxide spacer forming step.

22. The method according to claim 21 further comprising the steps of:

prior to the first spacer forming step, etching the portion of the substrate adjacent to the first buried contact to a level below the portion of the substrate beneath the first buried contact for defining a first generally vertical substrate wall;

thereafter, and prior to the first spacer forming step, implanting the substrate with the first impurity; and

wherein the substrate heating step further comprises the step of heating the substrate so that a continuous first impurity-doped region is formed beneath the first buried contact, adjacent the first substrate wall, and beneath the first oxide spacer.

23. The method according to claim 22 wherein the heating step further comprises the step of heating the substrate so that the portion of the first impurity-doped region beneath the buried contact is formed by out-diffusion of the first impurity from the thick polysilicon layer.

24. The method according to claim 23 wherein the heating step further comprises the step of heating the substrate so that the portion of the first impurity-doped region adjacent the substrate wall is formed by diffusion of the first impurity implanted in the substrate prior to the first spacer forming step.

25. The method according to claim 24 wherein the substrate implanting step performed prior to the first spacer forming step further comprises the step of tilting the substrate for increasing the amount of first impurity implanted in the first substrate wall.

26. A method of constructing a semiconductor structure comprising the steps of:

forming a bipolar region in a silicon substrate for a bipolar device, the bipolar region having a first region, termed a collector region, and a second region, the first and second regions being separated by a first field oxide region;

forming a first MOS region in the silicon substrate for a first channel type MOS device, the first MOS region being separated from the bipolar region by a second field oxide region;

forming a second MOS region in the silicon substrate for a second channel type MOS device, the second MOS region being separated from the first MOS region by a third field oxide region;

growing a thin oxide layer on the bipolar region and on the first and second MOS regions;

depositing a thin polysilicon layer over the thin oxide layer in the bipolar region and in the first and second MOS regions;

removing the thin polysilicon layer and the thin oxide layer from the second region and from regions of the substrate where first and second buried contacts to the substrate are to be made;

depositing a thick polysilicon layer on the bipolar region and on the first and second MOS regions;

masking a portion of the thick polysilicon layer in the second region for defining an emitter;

masking a portion of the thick polysilicon layer in the first MOS region for defining a first gate;

masking a portion of the thick polysilicon layer in the second MOS region for defining a second gate;

masking portions of the thick polysilicon layer for defining first and second interconnected buried contacts to the substrate;

etching the polysilicon in the bipolar and first and second MOS regions for forming an emitter of a bipolar device, a first gate for the first MOS device, a second gate for the second MOS device, and first and second interconnected polysilicon buried contacts to the substrate;

doping the portion of the polysilicon forming the first buried contact with a first impurity;

doping the portion of the substrate adjacent to the first buried contact with the first impurity;

doping the portion of the polysilicon forming the second buried contact with a second impurity;

doping the portion of the substrate adjacent to the second buried contact with the second impurity;

forming a first oxide spacer on a sidewall of the portion of the polysilicon forming the first buried contact;

forming a second oxide spacer on a sidewall of the portion of the polysilicon forming the second buried contact; and

heating the substrate so that a continuous first impurity-doped region is formed beneath the first buried contact and the first oxide spacer, and so that a continuous second imputity-doped region is formed beneath the second buried contact and the second oxide spacer.

27. The method according to claim 26 wherein the first and second impurities have the same conductivity type.

28. The method according to claim 26 wherein the first and second impurities have different conductivity types.

29. The method according to claim 26 wherein the step of doping the portion of the substrate adjacent to the first buried contact is performed after the first oxide spacer forming step.

30. The method according to claim 29 further comprising the steps of:

prior to the first spacer forming step, etching the portion of the substrate adjacent to the first buried contact to a level below the portion of the substrate beneath the first buried contact for defining a first generally vertical substrate wall;

thereafter, the prior to the first spacer forming step, implanting the substrate with the first impurity; and

wherein the substrate heating step further comprises the step of heating the substrate so that a continuous buried contact, adjacent the first substrate wall, and beneath the first oxide spacer.

31. The method according to claim 29 wherein the heating step further comprises the step of heating the substrate so that the portion of the first impurity-doped region beneath the buried contact is formed by out-diffusion of the first impurity from the thick polysilicon layer.

32. The method according to claim 31 wherein the heating step further comprises the step of heating the substrate so that the portion of the first impurity-doped region adjacent the substrate wall is formed by diffusion of the first impurity implanted in the substrate prior to the first spacer forming step.

33. The method according to claim 32 wherein the substrate implanting step performed prior to the first spacer forming step further comprises the step of tilting the substrate for increasing the amount of first impurity implanted in the first substrate wall.