Shared gate CMOS transistor

• US 5,083,190 A
• Filed: 12/17/1990
• Issued: 01/21/1992
• Est. Priority Date: 09/05/1989
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Pfiester, James R.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US07/628,821
• Time in Patent Office: 400 Days
• Field of Search: 357/237, 357/23.5, 357/23.14, 357/4, 357/42
• US Class Current: 257/369
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A stacked shared-gate CMOS transistor and method of fabrication are disclosed. An improved CMOS transistor is fabricated by the formation of a bulk transistor and an overlying isolated (SOI) transistor wherein each transistor is adjoined to a portion of a shared gate having the same conductivity type as the related transistor. The differential conductivity of the shared gate is obtained by the fabrication of a conductive diffusion-barrier layer intermediate to conductive layers. Improved switching performance is obtained as a result of higher current levels produced by the isolated transistor.

Claims

1. A CMOS semiconductor device having opposed N and P type channel regions electrically controlled by a shared gate electrode intermediate to the channel regions, the shared gate electrode comprising:

a first conductive region having an N-type impurity adjoining the N channel region;

a second conductive region having a P-type impurity adjoining the P channel region, wherein said first and second conductive regions form a common conductive layer; and

a conductive diffusion barrier selected from the group consisting of a refractory metal nitride and titanium carbide disposed within said common conductive layer separating said first and second conductive regions and preventing the diffusion of impurity atoms therethrough.

2. A semiconductor device having a bulk transistor and an isolated transistor comprising:

a first conductor of a first conductivity type overlying a thin dielectric layer disposed on the surface of a monocrystalline silicon substrate, said substrate having source and drain regions in said substrate on either side of said conductor and a first channel region therebetween;

a conductive diffusion-barrier overlying said first conductor;

a second conductor of a second conductivity type overlying said diffusion-barrier and aligned to said first conductor wherein, said second conductor, said conductive diffusion barrier, and said first conductor form a shared gate electrode;

an insulation layer overlying said shared gate electrode and extending over said source and drain regions in said substrate; and

a conductive layer of a second conductivity type overlying said insulation layer having heavily doped portions extending over and electrically insulated from said source and drain regions and a lightly doped portion directly overlying said shared gate electrode, wherein said lightly doped portion forms a second channel region and wherein said shared gate electrode provides voltage control for both said first and second channel regions;

whereby said conductive layer and said shared gate electrode comprise an isolated transistor and said source and drain regions, said first channel region and said shared gate electrode comprise a bulk transistor.

3. The semiconductor device of claim 2 wherein:

said first conductor of a first conductivity type comprises a conductor doped with an impurity atom to impart an N-type conductivity to said first conductor; and

said second conductor of a second conductivity type and said conductive layer comprise a conductor doped with an impurity atom to impart a P-type conductivity to said second conductor and said conductive layer.

4. The semiconductor device of claim 2 wherein:

said first conductor of a first conductivity type comprises a conductor doped with an impurity atom to impart a P-type conductivity to said first conductor; and

said second conductor of a second conductivity type and said conductive layer comprise a conductor doped with an impurity atom to impart an N-type conductivity to said second conductor and said conductive layer.

6. The semiconductor device of claim 2 wherein the conductive diffusion barrier comprises a material selected from the group consisting of a refractory metal nitride and titanium carbide.

5. A semiconductor device including a bulk N-type transistor and an isolated P-type transistor formed in a P-type semiconductor substrate comprising:

an N-type conductor overlying a central portion of an active region of said substrate, said N-type conductor being separated from said active region by a thin dielectric layer, wherein said N-type conductor and said dielectric layer overlie a first conductive channel in said active region, said first channel separating a first and a second heavily doped N-type region in said active region;

a conductive diffusion barrier layer overlying said N-type conductor;

a P-type conductor overlying said barrier layer, said P-type conductor, said barrier layer and said N-type conductor form a shared gate electrode wherein said conductors and said layers are aligned to each other in a vertical stack arrangement;

an continuous insulation layer overlying said P-type conductor and said active region;

a P-type conductive layer overlying said insulation layer, said P-type layer having a lightly doped portion directly overlying a central portion of said shared gate electrode and separated from said shared gate electrode by a thin portion of said insulation layer, said lightly doped portion forming a second conductive channel between a first and a second heavily doped portion of said P-type conductive layer, said first and second heavily doped portions forming the source and drain of a P-channel transistor respectively;

whereby said first and second heavily doped portions of said P-type conductive layer, said second conductive channel, said thin portion of said insulation layer, and said shared gate electrode form the source, drain, conductive channel, gate dielectric, and gate electrode respectively of an isolated P-channel transistor; and

whereby said first and second highly doped N-type regions, said first conductive channel, said dielectric layer, and said N-type conductor form the source, drain, conductive channel, gate dielectric, and gate electrode respectively of a bulk N-channel transistor, said first conductive channel being separated from said second conductive channel by said shared gate electrode where said shared gate electrode provides voltage control to both first and second conductive channels and said conductive diffusion barrier prevents the diffusion of dopant atoms between said N-type and said P-type conductors.

7. The semiconductor device of claim 5 wherein the conductive diffusion barrier comprises a material selected from the group consisting of a refractory metal nitride and titanium carbide.