Programmable multichannel hearing aid with adaptive filter

• US 5,083,312 A
• Filed: 08/01/1989
• Issued: 01/21/1992
• Est. Priority Date: 08/01/1989
• Status: Expired due to Term

• Current Assignee: Argosy Electronics
• Original Assignee: Argosy Electronics
• Inventors: Newton, James R., Preves, David A.
• Primary Examiner(s): Ng, Jin F.
• Assistant Examiner(s): Chan, Jason
• Application Number:
  US07/387,828
• Time in Patent Office: 903 Days
• Field of Search: 381/44, 381/68, 381/68.2, 381/68.4
• US Class Current: 381/320
• CPC Class Codes: H04R 2225/43 Signal processing in hearing aids to enhance the speech intelligibility
• CPC Class Codes: H04R 25/505 using digital signal processing
• CPC Class Codes: H04R 25/558 Remote control, e.g. of amplification, frequency

Abstract

A hearing aid is programmable with dual-tone multiple-frequency signals, received through the hearing aid microphone, to adjust operating coefficients of signal conditioning circuitry in the aid. A DTMF receiver filters and detects DTMF tone pairs into digital words provided to a controller for decoding, some of the digital words representing programming instructions and others representing data. In accordance with the instructions, the controller conveys the data to memory operatively associated with a plurality of control ports to the signal conditioning circuitry, with operating coefficients of the conditioning circuitry determined by the contents of the memory.

Claims

1. A signal processing circuit for a hearing aid, including:

a sound pressure level transducing means for sensing an audio signal and generating an electrical signal corresponding to said sensed audio signal, and a broadband signal amplifying means for amplifying said electrical signal to produce an amplified electrical signal;

a broadband detecting means for receiving a control input and for generating a control signal having a control signal level proportional to the level of said control input;

an adaptive high-pass filtering means, having as a first input said amplified electrical signal, and as a second input said control signal, for selectively suppressing a low frequency portion of said amplified electrical signal to generate a selectively modified signal, the frequency bandwidth of said suppressed low frequency portion, relative to the width of the entire frequency spectrum of said amplified electrical signal, increasing with said control signal level;

a plurality of restricted bandwidth filters, each receiving said modified signal and enhancing a selected portion of the frequency bandwidth of said modified signal to generate a selected bandwidth signal as its output, and a summing means for receiving said selected bandwidth signals as inputs, and for generating a combined signal based on the summation of said selected bandwidth signals;

an oscillator means for generating a clocking signal provided to each of said restricted bandwidth filters to determine a control frequency for each restricted bandwidth filter, and means for adjustably controlling said oscillator means to simultaneously adjust said control frequencies; and

a receiver means for generating an audio signal corresponding to said combined signal.

2. The signal processing circuit of claim 1 wherein:

said control input comprises said amplified electrical signal.

3. The signal processing circuit of claim 1 wherein:

said control input comprises said combined signal.

4. The signal processing circuit of claim 1 further including:

an anti-aliasing filter receiving said modified signal and providing its output to each of said restricted bandwidth filters.

5. The signal processing circuit of claim 4 further including:

sample and hold circuitry receiving the output of said anti-aliasing means, and providing its output as an input to each of said selective bandwidth filters.

6. The signal processing circuit of claim 5 wherein:

said means for adjustably controlling said oscillator means includes a clocking control means including a data storage means for storing one of a plurality of oscillator control settings for input to said oscillator means, and a control setting input means, operatively associated with said sound pressure level transducing means and said clocking control means, for providing a predetermined programming signal to said clocking control means responsive to the sensing of a predetermined audio signal by said sound pressure level transducing means, wherein said clocking control means, responsive to receiving said programming signal, selectively alters the oscillator control setting stored in said data storage means.

7. The signal processing circuitry of claim 1 further including:

a plurality of attenuator means, one associated with each of said restricted bandwidth filters, each for receiving its associated one of said selected bandwidth signals and controllably attenuating said signal to provide an attenuated bandwidth signal to said summing amplifier, whereby said combined signal is based on said attenuated signals.

8. The signal processing circuit of claim 7 further including:

a plurality of attenuator control means, one associated with each of said attenuator means, for adjustably determining the degree of attenuation of its associated attenuator means.

9. The signal processing circuit of claim 8 wherein:

each of said attenuator control means includes a data storage means for storing one of a plurality of attenuator control settings, and an attenuator control setting input means operatively associated with said sound pressure level transducing means, for providing a predetermined programming signal to said attenuator control means responsive to the sensing of a predetermined audio signal by said sound pressure level sensing means, wherein said attenuator control means, responsive to receiving said programming signal, selectively alters the attenuator control setting stored in said data storage means.

10. The signal processing circuit of claim 1 wherein:

said means for adjustably controlling said oscillator means comprises a clocking control means including a data storage means for storing one of a plurality of oscillator control settings for input to said oscillator means, and a control setting input means for providing a predetermined programming signal to said clocking control means, wherein said clocking control means, responsive to receiving said programming signal, selectively alters the oscillator control setting stored in said data storage means.

11. The signal processing circuit of claim 10 wherein:

said control setting input means is operatively associated with said sound pressure level transducing means and said clocking control means, and provides the predetermined programming signal to said clocking control means responsive to the sensing of a predetermined audio signal by said sound pressure level transducing means.

12. The signal processing circuit of claim 10 wherein:

said data storage means includes a nonvolatile, programmable digital memory for storing said control settings.

13. The signal processing circuit of claim 12 wherein:

said control settings include a plurality of current settings respectively relating to filter center frequencies, a peak clipping amplitude, a filter sensitivity, and a tone control of a variable cut-off frequency for an adaptive high-pass filter.

14. A signal processing circuit for a hearing aid, including:

a sound pressure level transducing means for sensing an audio signal and generating an electrical signal corresponding to said sensed audio signal, and a broadband signal amplifying means for amplifying said electrical signal to produce an amplified electrical signal;

a plurality of restricted bandwidth filters, each receiving said amplified electrical signal and enhancing a selected portion of the frequency bandwidth of said amplified electrical signal to generate a selected bandwidth signal as its output, and a summing means for receiving said selected bandwidth signals as inputs, and for generating a combined signal based on the summation of said selected bandwidth signals;

an oscillator means for generating a clocking signal, said clocking signal being provided to each of said restricted bandwidth filters to determine a control frequency for each restricted bandwidth filter, and means for adjustably controlling said oscillator means to simultaneously adjust said control frequencies;

a broadband detecting means for receiving a control input and for generating a control signal having a control signal level proportional to the level of said control input;

an adaptive high-pass filtering means, having as a first input said combined signal and as a second input said control signal, for selectively suppressing a low frequency portion of said combined signal to generate a selectively modified signal, the frequency bandwidth of said suppressed low frequency portion, relative to the width of the entire frequency spectrum of said combined electrical signal, increasing with said control signal level; and

a receiver means for generating an audio signal corresponding to said modified electrical signal.

15. The signal processing circuit of claim 14 wherein:

said control input comprises said amplified electrical signal.

16. The signal processing circuit of claim 14 wherein:

said control input comprises said combined signal.

17. The signal processing circuit of claim 14 wherein:

said restricted bandwidth filters include a low-pass filter, a high-pass filter and a bandpass filter, and wherein said control frequencies include a cut-off frequency for said high-pass filter, a cut-off frequency for said low-pass filter, and a center frequency for said bandpass filter.

18. The signal processing circuit of claim 14 wherein:

said means for adjustably controlling said oscillator means comprises a clocking control means including a data storage means for storing one of a plurality of oscillator control settings for input to said oscillator means, and a control setting input means for providing a predetermined programming signal to said clocking control means; and

wherein said clocking control means, responsive to receiving said programming signal, selectively alters the oscillator control setting stored in said data storage means.

19. The signal processing circuit of claim 18 wherein:

said control setting input means is operatively associated with said sound pressure level transducing means and said clocking control means, and provides the predetermined programming signal to said clocking control means responsive to the sensing of a predetermined audio signal by said sound pressure level transducing means.

20. The signal processing circuit of claim 18 wherein:

said data storage means includes a nonvolatile, programmable digital memory for storing said control settings.

21. The signal processing circuit of claim 20 wherein:

said control settings include a plurality of current settings respectively relating to filter center frequencies, a peak clipping amplitude, a filter sensitivity, and a tone control of a variable cut-off frequency for an adaptive high-pass filter.