Dynamic input sampling switch for CDACS

• US 5,084,634 A
• Filed: 10/24/1990
• Issued: 01/28/1992
• Est. Priority Date: 10/24/1990
• Status: Expired due to Term

• Current Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Original Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Inventors: Gorecki, James L.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Shingleton, Michael B.
• Application Number:
  US07/602,705
• Time in Patent Office: 461 Days
• Field of Search: 307/352, 307/353, 307/491, 307/572, 307/246
• US Class Current: 327/91
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 17/165 by feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A low distortion capacitor sampling circuit includes a sampling MOSFET, the source electrode of which receives a time-varying input voltage to be sampled. A bootstrap capacitor has a first terminal connected to the gate electrode of the sampling MOSFET and to a first MOSFET that charges the first terminal of the bootstrap capacitor to a first voltage in response to a first control signal. A delayed second control signal is applied to the gate of a second MOSFET the drain electrode of which is connected to a second terminal of the bootstrap capacitor to keep the pulldown MOSFET on until the charging of the sampling capacitor is complete. Then a third control signal turns on a third MOSFET, boosting both terminals of the bootstrap capacitor. The second control signal then turns the third MOSFET off, electrically isolating the gate electrode of the sampling MOSFET. Changes in the time-varying input voltage are coupled by the gate-to-source capacitance of the sampling MOSFET to the gate electrode thereof. The input voltage is simultaneously applied to a source follower circuit, the output of which is coupled by a CMOS transmission gate to the body electrode of the sampling MOSFET. The circuit avoids harmonic distortion due to modulation of channel resistance of the sampling MOSFET by keeping the gate-to-source voltage and the source-to-body electrode voltage independent of the input voltage.

Claims

1. A low distortion circuit for sampling an input voltage, comprising in combination:

(a) a sampling MOSFET having source, drain, gate, and body electrodes, the source electrode receiving the input voltage;

(b) a sampling capacitor having a first terminal coupled to the drain electrode and a second terminal connected to a grounding MOSFET;

(c) a bootstrap capacitor having a first terminal coupled by a first conductor to the gate electrode of the sampling MOSFET;

(d) first means coupled by the first conductor to the gate electrode of the sampling MOSFET for charging the first terminal of the bootstrap capacitor and the gate electrode to a first voltage, the first means producing a high impedance condition on the first conductor when the first voltage is attained;

(e) second means coupled to the second terminal of the bootstrap capacitor for applying a second voltage to the second terminal of the bootstrap capacitor during the charging of the first terminal of the bootstrap capacitor;

(f) third means for applying a third voltage to the second terminal of the bootstrap capacitor to produce a voltage on the first conductor equal to the first voltage plus the difference between the third and second voltages, and then producing a high impedance condition on the second terminal of the bootstrap capacitor, changes of the input voltage being capacitively coupled onto the first conductor by means of a gate-to-source capacitance of the sampling MOSFET; and

(g) a unity gain buffer having an input coupled to the input voltage and an output coupled to the body electrode of the sampling MOSFET,

whereby the gate-to-source voltage and the source-to-body voltage of the sampling MOSFET, and hence the channel resistance of the sampling MOSFET, are substantially independent of the changes of the input voltage.

2. The low distortion circuit of claim 1 wherein the first means includes a first MOSFET having a gate electrode coupled to a first control signal and a source electrode coupled to the first conductor.

3. The low distortion circuit of claim 2 wherein the first means includes a first CMOS inverter having an input coupled to the first control signal and an output coupled to the gate electrode of the first MOSFET.

4. The low distortion circuit of claim 3 wherein the first means includes a second CMOS inverter having an input coupled to the first control voltage and an output coupled to a body electrode of the first MOSFET, the second CMOS inverter including a P channel pullup MOSFET having a source electrode coupled to a ground conductor.

5. The low distortion circuit of claim 2 wherein the second means includes a second MOSFET having a source electrode coupled to a first supply voltage conductor, a drain electrode coupled to the second terminal of the bootstrap capacitor, and a gate electrode coupled to a signal delayed with respect to the first control signal to turn the second MOSFET off after the first conductor has been charged to the first voltage.

6. The low distortion circuit of claim 5 wherein the third means includes a third MOSFET having a source coupled to the second terminal of the bootstrap capacitor and a gate electrode coupled to a second control signal that occurs after the delayed signal to apply the third voltage to the second terminal of the bootstrap capacitor, the third control signal turning the third MOSFET off after the third voltage has been attained.

7. The low distortion circuit of claim 1 wherein the unity gain buffer includes a source follower MOSFET having a gate electrode coupled to the input voltage and a source electrode coupled to the body electrode of the sampling MOSFET.

8. The low distortion circuit of claim 7 wherein the source of the source follower MOSFET is coupled to the body electrode of the sampling MOSFET by means of a CMOS transmission gate controlled by the first control signal, wherein the low distortion circuit includes a MOSFET having a gate electrode coupled to the first control signal, a source electrode coupled to a supply voltage conductor, and a drain electrode coupled to the body electrode of the sampling MOSFET.

9. A low distortion method of sampling an input voltage, comprising the steps of:

(a) applying the input voltage to a source electrode of a sampling MOSFET and to an input of a unity gain buffer;

(b) applying an output signal produced by the unity gain buffer to a body electrode of the sampling MOSFET;

(c) applying a first control signal to a gate electrode of a first MOSFET having a source electrode coupled to a gate electrode of the sampling MOSFET and a first terminal of a bootstrap capacitor to charge the gate electrode of the sampling MOSFET and the first terminal to a first voltage;

(d) applying a voltage to a gate electrode of a second MOSFET having a source electrode coupled to a supply voltage conductor to maintain the second MOSFET in an on condition during step (c) and then applying another voltage to the gate electrode of the second MOSFET to turn it off after the first voltage has been attained;

(e) applying a third control voltage to a gate electrode of a third MOSFET having a source electrode coupled to the second terminal of the bootstrap capacitor to increase the voltage of the second terminal of the bootstrap capacitor by a second voltage to thereby boost the voltage of the gate electrode of the sampling MOSFET, and then removing the third control voltage to turn the third MOSFET off; and

(f) coupling changes of the input voltage onto the gate electrode of the sampling MOSFET by means of a gate-to-source capacitance of the sampling MOSFET,

whereby the gate-to-source voltage and the source-to-body voltage of the sampling MOSFET remain substantially constant and the channel resistance of the sampling MOSFET substantially independent of the input voltage.

10. The method of claim 9 including charging a sampling capacitor to the input voltage through the source and drain electrodes of the sampling MOSFET and a first terminal of the sampling capacitor while supplying a reference voltage to a second terminal of the sampling capacitor.

11. The method of claim 10 including applying the output voltage produced by the unity gain buffer through a CMOS transmission gate in response to the first control signal.