Bidirectional level shifting interface circuit

• US 5,084,637 A
• Filed: 05/30/1989
• Issued: 01/28/1992
• Est. Priority Date: 05/30/1989
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gregor, Roger P.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Bertelson, David R.
• Application Number:
  US07/358,321
• Time in Patent Office: 973 Days
• Field of Search: 307/475, 307/571, 307/242, 307/555, 307/542.1, 307/268, 307/471, 307/480, 307/241, 307/448, 307/243, 307/264, 340/825, 340/79, 340/146.2, 340/825.51, 340/825.52, 340/825.2, 340/825.62, 371/16.1, 371/16.4, 371/11.3, 365/233, 365/189.11, 455/51, 455/89, 455/99, 455/126, 455/127, 455/79, 375/7, 375/17-19
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018592 with a bidirectional operation

Abstract

A bidirectional level shifting interface circuit has first and second I/O ports and an FET with a drain-source channel connected between the first and second I/O ports. The first I/O port is connected to an I/O port of a first digital circuit operating at a relatively low supply voltage, and the second I/O port is connected to an I/O port of a second digital circuit operating at a relatively high supply voltage. This channel passes communication signals in each direction between the first and second digital circuit. A latching circuit comprising a P Channel FET is biased by the relatively high voltage supply, has an output connected to the second I/O port, and has a control input. The interface circuit further comprises an inverter circuit having a control input connected to the second I/O port and an inverted output connected to the control input of the latching FET such that when the second I/O port exhibits a binary one voltage caused by the first digital circuit, the inverted output exhibits a binary zero voltage to activate the P Channel FET to latch the second I/O port at sufficient voltage to drive the second digital circuit at binary one level.

Claims

1. A bidirectional level shifting interface circuit comprising:

first and second I/O ports;

a first FET having a channel connected between said first and second I/O ports, said first I/O port being including means for coupling to a third I/O port of a first digital circuit operating at a relatively low power supply voltage, and said second I/O port being including means for coupling to a fourth I/O port of a second digital circuit operating at a relatively high power supply voltage, said channel passing communication signals in each direction between said first and second digital circuits; and

latching circuit means, biased by the relatively high voltage power supply, having an output connected to said second I/O port, and having a control input responsive to the voltage at said first or second I/O ports, for latching said second I/O port at sufficient voltage to drive said second digital circuit at binary one level in response to the transmission by said first digital circuit of a binary one signal toward said second digital circuit via said first and second I/O ports.

2. An interface circuit as set forth in claim 1

wherein said latching circuit means comprises a P Channel FET and said control input is located at a gate of said P Channel FET and further comprising an inverter circuit having a control input connected to said second I/O port and an inverted output connected to said control input of said latching circuit means such that when said second I/O port exhibits a voltage greater than a threshold voltage of said inverter circuit caused by a binary one signal transmitted by said first digital circuit, said inverted output exhibits a binary zero voltage to activate said P Channel FET to latch said second I/O port at sufficient voltage to drive said second digital circuit at binary one voltage.

3. An interface circuit as set forth in claim 2 wherein said first FET has a gate biased by the relatively low voltage power supply, and an N channel.

4. An interface circuit as set forth in claim 3 further comprising a current sinking FET having a gate connected to the output of said inverter circuit and a channel connected between ground and each of said first and second I/O ports to sink load current when either of said digital circuits outputs a binary zero voltage.

5. An interface circuit as set forth in claim 2 wherein said inverter circuit comprises a P-Channel FET and an N-Channel FET having gates which are connected to one another and to said second I/O port, and channels which are connected in series, the output of said inverter circuit being located at the junction of said FET channels of the FETs within said inverter circuit.

6. An interface circuit as set forth in claim 1 wherein said first and second I/O ports are including means for coupling to said first and second digital circuits, respectively, via first and second transmission lines, respectively.

7. An interface circuit as set forth in claim 1 wherein said latching circuit means comprises an FET having a channel connected between said relatively high voltage power supply and said second I/O port, and a gate coupled to said second I/O port.

8. An interface circuit as set forth in claim 1 wherein the channel of said first FET is connected directly to said first and second I/O ports.

9. An interface circuit as set forth in claim 1 further comprising a first transmission line connected to said first I/O port and a second transmission line connected to said second I/O port.

10. An interface circuit as set forth in claim 9 wherein an on-resistance of said channel of said first FET is substantially less than the characteristic impedance of said first transmission line and said second transmission line.

11. A bidirectional communication system comprising:

a first digital circuit operating at a relatively low power supply voltage and having a first I/O port;

a second digital circuit operating at a relatively high power supply voltage and having a second I/O port;

a first transmission line connected at one end to said first I/O port;

a second transmission line connected at one end to said second I/O port; and

a bidirectional level shifting interface circuit comprising;

a third I/O port connected to the other end of said first transmission line;

a fourth I/O port connected to the other end of said second transmission line;

an FET having a channel connected between said third and fourth I/O ports; and

latching circuit means, biased by the relatively high voltage power supply, having an output connected to said fourth I/O port, and a control input responsive to the voltage at said third or fourth I/O ports for latching said fourth I/O port at sufficient voltage to drive said second digital circuit at binary one voltage in response to the transmission by said first digital circuit of a binary one signal toward said second digital circuit via said third and fourth I/O ports.

12. A communication system as set forth in claim 11 wherein

said first digital circuit comprises a first transceiver connected to said first I/O port, said first transceiver comprising a first transmitter, a first receiver, and first means for disabling said first transmitter during reception by said first receiver, said first transmitter when disabled exhibiting a substantially higher output impedance than when enabled to prevent loading of communication signals received by said first receiver;

and

said second digital circuit comprising a second transceiver connected to said second I/O port, said second transceiver comprising a second transmitter, a second receiver, and second means for disabling said second transmitter during reception by said second receiver, said second transmitter exhibiting a substantially higher output impedance when disabled than when enabled to prevent loading of communication signals received by said second receiver.

13. A communication system as set forth in claim 12 wherein said first transmitter of said first digital circuit exhibits an output impedance when enabled which output impedance is substantially less than a characteristic impedance of said first transmission line.

14. A communication system as set forth in claim 13 wherein said second transmitter of said second digital circuit exhibits an output impedance when enabled which output impedance is substantially greater that the output impedance exhibited by said first transmitter of said first digital circuit when enabled.

15. A system as set forth in claim 12

wherein said latching circuit means of said interface circuit comprises a P Channel FET, and said control input is located at a gate of said P Channel FET, and

said interface circuit further comprises an inverter circuit having a control input connected to said fourth I/O port, and an inverted output connected to said control input of said latching circuit means such that when said fourth I/O port exhibits a voltage greater then a threshold voltage of said inverter circuit caused by a binary one signal transmitted by said first digital circuit, said inverted output exhibits a binary zero voltage to activate said P Channel FET to latch said fourth I/O port at sufficient voltage to drive said second digital circuit at binary one voltage.

16. A system as set forth in claim 11 wherein said FET has a gate biased by the relatively low voltage power supply, and an N Channel.

17. A system as set forth in claim 15 wherein said interface circuit further comprises a current sinking FET having a gate connected to the output of said inverter circuit and a channel connected between said third I/O port and ground to sink load current when one of said digital circuits outputs a binary zero voltage.

18. A system as set forth in claim 15 wherein said inverter circuit comprises a P-Channel FET and an N-Channel FET having gates which are connected to one another and to said fourth I/O port, and channels which are connected in series, the output of said inverter circuit being located at the junction of said FET channels of the FETs within said inverter circuit.

19. An interface circuit as set forth in claim 11 wherein the channel of said FET is connected directly to said third and fourth I/O ports.

20. An interface circuit as set forth in claim 19 wherein an on-resistance of said channel of said FET is substantially less than a characteristic impedance of said first transmission line and said second transmission line.

21. A bidirectional communication system as set forth in claim 11 wherein:

said first digital circuit comprises a transmitter having an output connected to said first I/O port, and

said second digital circuit comprises a receiver having an input connected to said second I/O port, said receiver exhibiting a substantially higher input impedance than a characteristic impedance of said second transmission line such that when said transmitter transmits a binary one signal to said receiver via said first, third, fourth and second I/O ports and said first and second transmission lines, the voltage of said binary one signal increases at the input of said receiver to exceed a threshold voltage of said receiver, the voltage of the binary one signal transmitted from said transmitter along said second transmission line being less than said threshold voltage before said increase at the input of said receiver, said binary one signal causing a reflection at the input of said receiver, said reflection activating said control input of said latching circuit means to latch said forth I/O port at sufficient voltage to drive said second digital circuit at binary one voltage.