Direct phase digitization

• US 5,084,669 A
• Filed: 03/08/1990
• Issued: 01/28/1992
• Est. Priority Date: 03/08/1990
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Dent, Paul W.
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): Solis, Jose M.
• Application Number:
  US07/490,330
• Time in Patent Office: 691 Days
• Field of Search: 328/133, 328/134, 328/155, 328/141, 324/83 R, 324/83 D, 307/514, 307/516
• US Class Current: 324/76.82
• CPC Class Codes: H03D 13/006 and by sampling this signal by narrow pulses obtained from the second oscillation

Abstract

An electrical circuit for producing a digital value which is representative of instantaneous phase of an electrical input signal relative to a reference frequency signal. The circuit includes a digital counter for continuously generating a stored count representing a value resulting from dividing the reference frequency signal by a repeating count cycle frequency which is of the same order as an expected center frequency of the electrical input signal. A trigger unit produces a trigger pulse in response to the trigger unit receiving a sampling pulse and a transition edge of the electrical input signal. An intermediate register stores a momentary state of the counter circuit in response to receiving the trigger pulse. The momentary state of the counter circuit corresponds to an instantaneous phase value of the electrical input signal. A correcting circuit is provided for correcting a resulting numerical value in the intermediate register by removing an accumulating phase offset value. An output register is provided for storing the corrected resulting numerical value of the counter circuit.

Claims

1. An electrical circuit for determining at specified sampling instants a numerical value which represents as a digital code an instantaneous phase of an electrical signal relative to a reference frequency signal, said circuit comprising:

counter means for continuously generating a stored count representing a value resulting from dividing said reference frequency signal by a repeating count cycle frequency, said count cycle repetition frequency being of the same order as an expected center frequency of said electrical signal;

trigger means for producing a trigger pulse in response to receiving a sampling pulse and a transition of said electrical signal; and

first register means for storing a momentary state of said counter means, said momentary state of said counter means being transferred to said first register means in response to said first register means receiving said trigger pulse, said momentary state corresponding to an instantaneous phase value of said electrical signal.

2. An electrical circuit according to claim 1 further comprising:

correcting means for correcting a resulting numerical value in said first register means by removing accumulating phase offset value, said phase offset value being a product of a predetermined time period between sampling pulses and a predetermined frequency difference between said count cycle repetition frequency and said expected center frequency of said electrical signal; and

second register means for storing said corrected resulting numerical value of said counter means which is transferred from said first register means in response to an occurrence of a next sampling pulse, said occurrence of said next sampling pulse effecting a storage of a next momentary state of said counter means in said first register means.

3. An electrical circuit according to claim 2, wherein said trigger means comprises:

a first transition triggered device which is set in response to receiving said sampling pulse and producing a set signal; and

a second transition triggered device which is set in response to receiving said transition of said electrical signal, and wherein

said trigger pulse is produced by said second transition triggered device in response to said second transition triggered device receiving both said set signal from said first transition triggered device and said transition of said electrical signal, said trigger pulse effecting a reset of said first and second transition triggered devices.

4. An electrical circuit according to claim 3, wherein said first and second transition triggered devices comprise flip-flops.

5. An electrical circuit according to claim 3, further comprising:

second trigger means for producing a second trigger pulse in response to receiving said sampling pulse and a second transition of said electrical signal, said second transition being opposite to said transition of said electrical signal received at said second input of said trigger means;

third register means for storing said momentary state of said counter means, said momentary state of said counter means being transferred to said third register means in response to said third register means receiving said second trigger pulse; and

means for combining contents of said first register means and said third register means in order to produce an output value.

6. An electrical circuit according to claim 2, wherein said correcting means comprises a digital accumulator having contents which are incremented between sampling pulses by a value which is proportional to said product of said predetermined time period and said predetermined frequency difference, said accumulator contents being added to or subtracted from said measured phase value in order to remove said accumulating phase offset.

7. An electrical circuit according to claim 2, further comprising means to produce a digital code which represents an instantaneous frequency of said electrical signal, said means to produce being operable for subtraction of two successive instantaneous phase values using modulo 2Pi arithmetic.

8. An electrical circuit according to claim 1, wherein said trigger means comprises:

a first trigger circuit for producing a first partial trigger pulse in response to receiving said sampling pulse and a positive going transition of said electrical signal;

a second trigger circuit for producing a second partial trigger pulse in response to receiving said sampling pulse and a negative going transition of said electrical signal

an OR circuit for passing either of said first or second partial trigger pulses as said trigger pulse; and

a flip-flop which produces a correction signal in response to said trigger pulse being produced in accordance with said second trigger circuit receiving said negative going transition of said electrical signal.

9. An electrical circuit according to claim 8, further comprising correcting means for correcting said momentary state of said counter means being stored in said first register means by 180°

in response to receiving said correction signal.

10. An electrical circuit according to claim 9, wherein said correcting means comprises an XOR circuit for inverting the most significant bit of said momentary state.

11. An electrical circuit according to claim 2, further comprising a second correcting means coupled to said second register means for correcting said resulting numerical value for a timing error introduced by variations in said trigger pulse relative to said sampling pulse with a correction factor being proportional to a product of said timing error and an estimate of an instantaneous frequency value associated with said resulting numerical value.

12. An electrical circuit according to claim 11, further comprising a frequency estimator means coupled to said second correcting means for generating said instantaneous frequency value associated with said resulting numerical value.

13. An electrical circuit according to claim 12, wherein said frequency estimator means comprises a digital phase-lock-loop circuit.

14. An electrical circuit according to claim 12, wherein said frequency estimator means comprises a subtractor means for producing a difference between phase values occurring a predetermined number of sampling periods apart.

15. An electrical circuit according to claim 1, wherein said counter means produces a Grey coded counter sequence.

16. An electrical circuit according to claim 15, further comprising a Grey-to-binary converter coupled between said first register means and said second register means.

17. An electrical circuit for producing a digital value which is representative of an instantaneous phase of an input signal relative to a reference frequency, said circuit comprising:

a digital counter which continuously generates a stored count representing a value resulting from dividing said reference frequency by a repeating count cycle frequency;

a trigger circuit which produces a trigger pulse in response to being armed by a sampling pulse and being fired by a zero-crossing transition of said input signal; and

a first storage latch for storing said value generated by said digital counter in response to receiving said trigger pulse, said stored value corresponding to an instantaneous phase value of said input signal.

18. An electrical circuit according to claim 17 further comprising:

a digital accumulator which is incremented at every occurrence of said sampling pulse by a predetermined phase error value, said phase error value being a product of a predetermined time period between sampling pulses and a predetermined frequency difference between said repeating count cycle frequency and an expected center frequency of said input signal;

a digital adder/subtractor which removes said phase error value from said stored value and produces a corrected phase value; and

an output storage latch for storing said corrected phase value in response to an occurrence of a next sampling pulse.

19. An electrical circuit according to claim 17, wherein said first storage latch includes a dedicated bit for recording whether said reference frequency was on a negative or positive half cycle when said trigger pulse is produced.

20. An electrical circuit according to claim 17, wherein said trigger circuit comprises:

a first flip-flop which produces a set signal in response to receiving a high signal from a constant high signal source and said sampling pulse;

a second flip-flop which produces said trigger pulse in response to receiving said set signal and said zero-crossing transition of said input signal; and

a delay circuit for producing a delayed reset pulse from said trigger pulse, said first and second flip-flops being simultaneously reset in response to receiving said delayed reset pulse.

21. An electrical circuit according to claim 17, further comprising:

a secondary trigger circuit which produces a second trigger pulse in response to receiving said sampling pulse and another zero-crossing transition of said input signal, said other zero-crossing transition being of opposite polarity to said zero-crossing transition of said input signal;

a second storage latch for storing another value of said counter circuit in response to receiving said second trigger pulse; and

a combining circuit which combines contents of said first storage latch and said second storage latch to produce a phase representation value.

22. An electrical circuit according to claim 21, wherein said combining circuit combines the contents of said first and second storage latches by performing the following equation:

space="preserve" listing-type="equation">PRV=MOD2n(2A+MODn(B-A))

where n is an integer, A is the content of said first storage latch, B is the content of said second storage latch, and PRV is the phase representation value produced.

23. An electrical circuit according to claim 17, further comprising means to produce a digital code which represents an instantaneous frequency of said input signal, said means for producing being operable for subtraction of two successive instantaneous phase values of said input signal using modulo 2Pi arithmetic.

24. An electrical circuit according to claim 17, wherein said trigger circuit comprises:

a positive transition trigger circuit which produces a positive transition trigger pulse in response to receiving said sampling pulse and a positive going transition of said input signal;

a negative transition trigger circuit which produces a negative transition trigger pulse in response to receiving said sampling pulse and a negative going transition of said input signal;

an OR gate for passing either said positive transition trigger pulse or said negative transition trigger pulse as said trigger pulse;

a flip-flop which produces a correction signal in response to said trigger pulse being produced in accordance with said negative transition trigger circuit receiving said negative going transition of said electrical signal.

25. An electrical circuit according to claim 24, further comprising correcting means for correcting said stored value of said first storage latch by 180°

in response to receiving said correction signal.

26. An electrical circuit according to claim 25, wherein said correcting means comprises an XOR gate for inverting the most significant bit of said stored value.

27. An electrical circuit according to claim 17, further comprising a second correcting means coupled to said output storage latch for correcting said phase value for a timing error introduced by variations in said trigger pulse relative to said sampling pulse with a correction factor, said correction factor being proportional to a product of said timing error and an estimate of an instantaneous frequency value associated with said phase value.

28. An electrical circuit according to claim 27, further comprising a frequency estimator means coupled to said second correcting means for generating said instantaneous frequency value associated with said phase value.

29. An electrical circuit according to claim 28, wherein said frequency estimator means comprises a digital phase-lock-loop circuit.

30. An electrical circuit according to claim 28, wherein said frequency estimator means comprises a subtractor means for producing a difference between phase values occurring a predetermined number of sampling periods apart.

31. An electrical circuit according to claim 17, wherein said counter means produces a Grey coded counter sequence.

32. An electrical circuit according to claim 31, further comprising a Grey-to-binary converter coupled between said intermediate latch and said output latch.

33. A method for producing a digital value which is representative of an instantaneous phase of an input signal relative to a reference frequency, comprising the steps of:

continuously generating a stored count representing a value resulting from dividing said reference frequency by a repeating count cycle frequency;

producing a trigger pulse in response to an occurrence of a sampling pulse and a zero-crossing transition of said input signal; and

storing said value generated in response to receiving said trigger pulse, said stored value of said input signal.

34. A method according to claim 33 further comprising the steps of:

incrementing a digital accumulator at every occurrence of said sampling pulse by a predetermined phase error value, said phase error value being a product of a predetermined time period between sampling pulses and a predetermined frequency difference between said repeating count cycle frequency and an expected center frequency of said input signal;

removing said phase error value from said stored value and producing a corrected phase value; and

storing said corrected phase value in response to an occurrence of a next sampling pulse.

35. A method according to claim 33 further comprising the step of recording whether said reference frequency was on a negative or positive half cycle when said trigger pulse is produced.

36. A method according to claim 33 further comprising the steps of:

producing a second trigger pulse in response to receiving said sampling pulse and another zero-crossing transition of said input signal, said other zero-crossing transition being of opposite polarity to said zero-crossing transition of said input signal;

storing another value generated in response to receiving said second trigger pulse; and

combining contents being stored to produce a phase representation value.

37. A method according to claim 36 wherein said step of combining said contents being stored further comprises the step of performing the following equation:

space="preserve" listing-type="equation">PRV=MOD2n (2A+MODn(B-A))

where n is an integer, A is the value stored in response to said trigger pulse, B is the value stored in response to said second trigger pulse, and PRV is the phase representation value produced.

38. A method according to claim 33 further comprising the step of producing a digital code which represents an instantaneous frequency of said input signal, said producing step including subtracting two successive instantaneous phase values of said input signal using modulo 2Pi arithmetic.

39. A method according to claim 34 further comprising the step of correcting said phase value for a timing error introduced by variations in said trigger pulse relative to said sampling pulse with a correction factor, said correction factor being proportional to a product of said timing error and an estimate of an instantaneous frequency value associated with said phase value.

40. A method according to claim 39 further comprising the step of generating an estimate of said instantaneous frequency value associated with said phase value.

41. A method according to claim 40 wherein said generating step further includes the step of producing a difference between phase values occurring a predetermined number of sampling periods apart.