Simulation model generation from a physical data base of a combinatorial circuit

• US 5,084,824 A
• Filed: 03/29/1990
• Issued: 01/28/1992
• Est. Priority Date: 03/29/1990
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Lalchandani, Amrit K., Lam, Nim C.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/502,581
• Time in Patent Office: 670 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 371/23
• US Class Current: 716/103
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A design layout sequence for an application specific integrated circuit such as an ECL gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing step which results in a number of various files defining, for example bias drivers, I/O macros, and relationships between chip pads and I/O signals. The design layout sequence culminates in a physical data base file. To ensure a functional design, the designer'"'"'s work is simulated after both schematic capture and placement and routing using a library containing simulation models for each type of macrocell used in the design. The gate-level netlist component of the simulation models are created automatically in a computer-implemented technique that identifies each root in the combinatorial circuit, assigns each a logical value, and traverses the tree that originates from each identified root. As each tree is traversed, Boolean equations identifying the logical values at each node encountered are determined in accordance with a set of relationships pertinent to the standard circuit elements and a set of logic value assignment definitions. The resulting set of Boolean equations is used to construct the gate-level netlist that is incorporated into the simulation model of the macrocell.

Claims

1. A method for generating a gate-level netlist for a macrocell simulation model from a physical layout of said macrocell, comprising the steps of:

generating a circuit-level netlist from a physical layout of said macrocell;

identifying each true root present in said circuit-level netlist;

for each true root identified, identifying from said circuit-level netlist successive circuit nodes of a tree associated therewith;

for each of said successive circuit nodes of a tree, successively determining a respective Boolean equation based on circuit elements connected thereto, in accordance with a set of relationship rules pertinent to circuit elements of said macrocell and a set of logical value assignment definition rules, said identified circuit nodes including a set of output nodes; and

converting the Boolean equation for said set of output nodes into a gate-level netlist.

2. A method as in claim 1, wherein said Boolean equation conversion step comprises the step of converting said Boolean equations into a set of logical operator expressions.

3. A method as in claim 2, wherein said Boolean equation conversion step further comprising the step of reducing said logical operator expressions.

4. A method as in claim 3, wherein said Boolean equation conversion step further comprises the steps of:

generating a first truth table from said set of logical operator expressions;

generating a second truth table from said reduced set of logical operator expressions; and

comparing said first and second truth tables to confirm the reduction.

5. A method as in claim 1, further comprising the steps of:

generating a truth table from the Boolean equations for said set of output nodes; and

comparing said generated truth table to a known correct truth table to confirm the Boolean equations for said set of output nodes.

6. A method as in claim 1, wherein said step of identifying from said circuit-level netlist successive circuit noes of a tree comprises traversing said tree in a depth-first traversal.

7. A method as in claim 1, wherein said step of identifying from said circuit-level netlist successive circuit nodes of a tree comprises traversing said tree in a breadth-first traversal.

8. A method as in claim 1, wherein:

said relationship rules are relationship rules pertinent to a transistor and resistor of an ECL-type circuit, and specify that;

for a resistor having two terminals, the terminal closest said root is the "father" and the other terminal is the "son;

" and

for a transistor having three terminals, the emitter terminal is the "father," the base terminal is the "daughter," and the collector terminal is the "son;

" and

said logical value assignment definition rules are definition rules pertaining to an ECL-type circuit, and specify that;

for a resistor, the logical value of the son equals the logical value of the father;

for a transistor, the logical value of the collector equals the AND of the logical value of the emitter and the logical value of the base;

the logical value of a root is ONE;

the logical value of a bias signal for a current source equals ONE;

the logical value of a bias signal for a current switch equals the complement of the logical value of the base of a switching transistor associated with said current switch;

the logical value of a supernode equals the OR of the logical values of all collectors tied to said supernode;

the logical value of an input translator with plural inputs equals the OR of the logical values of said plural inputs; and

the logical value of an output node equals the complement of the logical value of a base of a transistor associated with said output node.

9. A method as in claim 1, further comprising the step of preprocessing said circuit-level netlist prior to said circuit node identifying step, said Boolean equation determining step, and said Boolean equation conversion step.

10. A method as in claim 9, wherein said preprocessing step comprises the steps of:

extracting parallel transistors and resistors;

preprocessing output emitter followers; and

preprocessing input transistors.

11. An apparatus for generating a gate-level netlist for a macrocell simulation model from a physical layout of said macrocell, comprising:

a data storage device for storing a physical layout of said macrocell;

means for generating a circuit-level netlist from said physical layout of said macrocell accessed from said data storage device;

means for identifying each true root present in said circuit-level netlist;

means for identifying from said circuit-level netlist, for each true root identified, successive circuit nodes of a tree associated therewith;

means for successively determining, at each of said successive circuit nodes, a Boolean equation based on circuit elements connected thereto, in accordance with a set of relationship rules pertinent to circuit elements of said macrocell and a set of logical value assignment definition rules, said identified circuit nodes including a set of output nodes; and

means for converting the Boolean equations for said set of output nodes into a gate-level netlist.