Semiconductor memory having control means for preventing unauthorized erasure of a memory array portion

• US 5,084,843 A
• Filed: 04/24/1990
• Issued: 01/28/1992
• Est. Priority Date: 03/16/1987
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Matsubara, Kiyoshi, Ozawa, Yoshiyuki, Takamori, Yoh, Mitsuishi, Naoki
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): Ray, Gopal C.
• Application Number:
  US07/513,569
• Time in Patent Office: 644 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 365/218, 365/195, 365/189.01, 365/228
• US Class Current: 365/218
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A volatile storage circuit for latching data is disposed outside a non-volatile memory array. Before a bulk erase of the memory array, some of the data items contained therein are transferred to and held by the storage circuit. The data items thus saved are rewritten to the non-volatile memory array after the bulk erase, or alternatively, on the basis of control data items transferred to the storage circuit, only regions designated by these data items are subjected to the bulk erase. Thus, in case of a bulk erase of an EEPROM, some of the stored data items can be preserved, so as to prevent illicit use of and maintain the integrity of the preserved data. Also the testing time of the data rewritten to the memory array is reduced because of the elimination of the need to test the memory area containing the preserved data in that only the integrity of the memory area containing data sourced externally need be tested.

Claims

1. A single-chip microcomputer having a non-volatile memory and a central processing unit coupled to the non-volatile memory and to a random access memory, the non-volatile memory comprising:

a memory array comprising a first group of non-volatile memory cells and a second group of non-volatile memory cells;

electrical erasure means for executing an erasure operation on said memory array;

selecting means, coupled to said memory array, for selecting a non-volatile memory cell from said memory array;

designating means, coupled to the electrical erasure means, for designating whether the selected non-volatile memory cell is in the first group of non-volatile memory cells or in the second group of non-volatile memory cells;

control register means, coupled to the electrical erasure means, for controlling the erasure operation of the electrical erasure means on said memory array including a first control bit means, the firsts control bit means having a first state for inhibiting the eraser operation of the electrical erasure means on the memory array and a second state for enabling the erasure operation of the electrical erasure means on the memory array; and

,

erase inhibit override means for inhibiting the erasure operation of the electrical erasure means on the second group of non-volatile memory cells regardless of the second state of the first control bit means when the designating means designates that the selected non-volatile memory cell is in the second group of non-volatile memory cells.

2. The single-chip microcomputer according to claim 1, further comprising:

an interface circuit coupled to the central processing unit; and

,

an external access terminal means, coupled to the non-volatile memory, for accessing the non-volatile memory.

3. The single-chip microcomputer according to claim 2, wherein the interface circuit comprises communication means for sending data to and receiving data from a device external to the single-chip microcomputer, and wherein the single-chip microcomputer further includes a read only memory means for storing a program.

4. The single-chip microcomputer according to claim 2, further comprising:

an external control terminal means for receiving a control signal; and

,

mode setting means, coupled to the external control terminal, for delivering a mode signal representative of whether said non-volatile memory is accessed by the central processing unit or accessed externally via said eternal access terminal means based on the control signal received.

5. The single-chip microcomputer according to claim 1, wherein the non-volatile memory further comprises writing means for executing a writing operation to said memory array, and wherein the control register means further comprises a second control bit means for controlling the writing operation of the writing means to said memory array, the second control bit means having a first state for inhibiting the writing operation of the writing means to said memory array, and a second state for enabling the writing operation of the writing means to said memory array, the states of said second control bit means being determined by said central processing unit.

6. The single-chip microcomputer according to claim 5, wherein said central processing unit comprises means for determining the first and second states of said second control bit means.

7. The single-chip microcomputer according to claim 1, wherein the central processing unit comprises means for determining said first and second states of the first control bit means.

8. The single-chip microcomputer according to claim 1, wherein said non-volatile memory comprises a plurality of non-volatile memory cells, each cell being an electrically erasable and programmable memory element.

9. An integrated circuit card comprising a single-chip microcomputer having a non-volatile memory and a central processing unit coupled to the non-volatile memory and to a random access memory, the non-volatile memory comprising:

a memory array comprising a first group of non-volatile memory cells and a second group of non-volatile memory cells;

electrical erasure means for executing an erasure operation on said memory array;

selecting means, coupled to said memory array, for selecting a non-volatile memory cell from said memory array;

designating means, coupled to the electrical erasure means, for designating whether the selected non-volatile memory cell is in the first group of non-volatile memory cells or in the second group of non-volatile memory cells;

control register means, coupled to the electrical erasure means, for controlling the erasure operation of the electrical erasure means on said memory array including a first control bit means, the firsts control bit means having a first state for inhibiting the eraser operation of the electrical erasure means on the memory array and a second state for enabling the erasure operation of the electrical erasure means on the memory array; and

,

erase inhibit override means for inhibiting the erasure operation of the electrical erasure means on the second group of non-volatile memory cells regardless of the second state of the first control bit means when the designating means designates that the selected non-volatile memory cell is in the second group of non-volatile memory cells.

10. The integrated circuit card according to claim 9, wherein the non-volatile memory further comprises writing means for executing a writing operation to said memory array, and wherein the control register means further comprises a second control bit means for controlling the writing operation of the writing means to said memory array, the second control bit means having a first state for inhibiting the writing operation of the writing means to said memory array, and a second state for enabling the writing operation of the writing means to said memory array.

11. The integrated circuit card according to claim 10, wherein said central processing unit comprises means for determining the first and second states of said first control bit means.

12. The integrated circuit card according to claim 11, wherein the central processing unit comprises means for determining the first and second states of said second control bit means.

13. The integrated circuit card according to claim 9, wherein the central processing unit comprises means for determining said first and second states of the first control bit means.

14. The integrated circuit card according to claim 9, wherein said non-volatile memory comprises a plurality of non-volatile memory cells, each cell being an electrically erasable and programmable memory element.