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Semiconductor memory having control means for preventing unauthorized erasure of a memory array portion

  • US 5,084,843 A
  • Filed: 04/24/1990
  • Issued: 01/28/1992
  • Est. Priority Date: 03/16/1987
  • Status: Expired due to Term
First Claim
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1. A single-chip microcomputer having a non-volatile memory and a central processing unit coupled to the non-volatile memory and to a random access memory, the non-volatile memory comprising:

  • a memory array comprising a first group of non-volatile memory cells and a second group of non-volatile memory cells;

    electrical erasure means for executing an erasure operation on said memory array;

    selecting means, coupled to said memory array, for selecting a non-volatile memory cell from said memory array;

    designating means, coupled to the electrical erasure means, for designating whether the selected non-volatile memory cell is in the first group of non-volatile memory cells or in the second group of non-volatile memory cells;

    control register means, coupled to the electrical erasure means, for controlling the erasure operation of the electrical erasure means on said memory array including a first control bit means, the firsts control bit means having a first state for inhibiting the eraser operation of the electrical erasure means on the memory array and a second state for enabling the erasure operation of the electrical erasure means on the memory array; and

    ,erase inhibit override means for inhibiting the erasure operation of the electrical erasure means on the second group of non-volatile memory cells regardless of the second state of the first control bit means when the designating means designates that the selected non-volatile memory cell is in the second group of non-volatile memory cells.

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