Automated system for extracting design and layout information from an integrated circuit

• US 5,086,477 A
• Filed: 08/07/1990
• Issued: 02/04/1992
• Est. Priority Date: 08/07/1990
• Status: Expired due to Term

• Current Assignee: Technology Group Northwest Incorporated
• Original Assignee: Northwest Technology Center Incorporated
• Inventors: Yu, Kenneth K., Berglund, C. Neil
• Primary Examiner(s): Boudreau, Leo H.
• Assistant Examiner(s): Johns, Andrew W.
• Application Number:
  US07/564,175
• Time in Patent Office: 546 Days
• Field of Search: 382/8, 382/56, 364/522, 364/489, 364/490, 364/491, 358/101, 358/107
• US Class Current: 382/145
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits

Abstract

A system for extracting design information from a semiconductor integrated circuit (IC) is disclosed. The system includes a microscope and camera for capturing a composite image of the IC in the form of a video signal. Image capture occurs on a section-by-section basis in which a "snapshot" of each section is taken, the die-holding table stepped to a new section, and a snapshot of the new section obtained. This image capture operation continues until a composite image of the IC is obtained by successive capture of contiguous or partially overlapping images covering all of the different sections of the die. An image processor receives the video signal from the optical means and generates an abstract representation of the die in the form of lists of identifying features such as the size, type and relative location of all transistors, and the width, length and relative location of all of the metal interconnects to the IC. These lists are subsequently compared with reference library circuits by a computer to recognize individual circuit cells. Once all of the ciruit cells on the die have been recognized, the computer then generates a schematic netlist of the IC.

Claims

1. A system for extracting design information from a semiconductor integrated circuit (IC) comprising:

means for capturing the image of a section of said IC in the form of a video signal;

table means for placing said IC in position for image capture of said section by said capture means, said table means being responsive to a control signal to enable said IC to be repositioned relative to said capture means such that a composite image of said IC can be obtained by successive capture of partially contiguous or overlapping images covering all of the different sections of said IC;

image processing means for receiving said video signal and for generating an abstract representation of said images, said abstract representation including lists of identifying features of each of said sections and the relative locations of said identifying features;

memory means for storing said images, said abstract representations and a reference library of circuit elements;

computer means coupled to said image processing and memory means for combining said abstract representations of said images to obtain said composite image, and for recognizing individual circuit cells by matching the abstract representation of a portion of said composite image with a corresponding entry in said reference library;

once all of said circuit cells on said IC have been recognized, said computer means generating a schematic representation of said IC in the form of a netlist.

2. The system of claim 1 wherein said composite image contains abstract representations extracted from multiple fabrication layers of said IC.

3. The system of claim 2 wherein said computer system further comprises a means for correlating said multiple layers and for registering them to each other.

4. The system of claim 3 wherein said correlation means comprises a grid coordinate system overlaid over said composite image and referenced to a point of origin which is identically located on each of said multiple layers.

5. The system of claim 4 wherein said computer means provides said control signal to said table means during image capture.

6. The system of claim 5 wherein said table means comprises a motorized X-Y table.

7. The system of claim 3 wherein said capture means comprises a microscope and video camera mechanism.

8. The system of claim 7 wherein said image processing means is capable of operating on said video signal to enhance the contrast between said multiple layers of said IC.

9. The system of claim 8 wherein said computer means builds said composite image by matching said identifying features at the boundaries of adjacent sections of said partially overlapping images for each of said multiple layers of said IC.

10. The system of claim 9 wherein said image processing means comprises a digitizer for producing a digital image from said video signal.

11. The system of claim 10 wherein each pixel of said digital image contains information from no more than one third of the minimum size of any feature being captured on said IC.

12. The system of claim 11 wherein said microscope and camera mechanism has a resolution capable of distinguishing 500 individual pixels in both the X and Y directions.

13. A system for extracting design information from a semiconductor integrated circuit (IC) comprising:

optical means for capturing the image of a section of said IC in the form of a video signal;

table means for placing said IC in position for image capture of said section by said optical means, said table means being responsive to a control signal to enable said IC to be positioned relative to said optical means such that a composite image of said IC can be obtained by successive capture of contiguous or partially overlapping images covering all of the different sections of said IC;

image processing means for receiving said video signal and for generating an abstract representation of said images, said abstract representation including lists of identifying features of each of said sections and the relative locations of said identifying features;

memory means for storing said images, said abstract representations and a reference library of circuit elements;

computer means coupled to said image processing and memory means for combining said abstract representations of said images to obtain said composite image, and for recognizing individual circuit cells by using their abstract representations to identify circuit components within said cells and to decipher their interconnections therefrom, each of said recognized cells being input into said reference library for subsequent recognition of other instances of said cells;

once all of said circuit cells on said IC have been recognized, said computer means generating a schematic representation of said IC in the form of a netlist.

14. The system of claim 13 wherein said composite image contains abstract representations extracted from multiple fabrication layers of said IC.

15. The system of claim 14 wherein said computer system further comprises a means for correlating said multiple layers and for registering them to each other.

16. The system of claim 15 wherein said correlation means comprises a grid coordinate system overlaid over said composite image and referenced to a point of origin which is identically located on each of said multiple layers.

17. The system of claim 16 wherein said computer means provides said control signal to said table means during image capture.

18. The system of claim 17 wherein said table means comprises a motorized X-Y table.

19. The system of claim 18 wherein said optical means comprises a microscope and video camera mechanism.

20. The system of claim 16 wherein said image processing means is capable of operating on said video signal to enhance the contrast between said multiple layers of said IC.

21. The system of claim 20 wherein said computer means builds said composite image by matching said identifying features at the boundaries of adjacent sections of said contiguous or partially overlapping images for each layer of said IC.

22. The system of claim 21 wherein said image processing means comprises a digitizer for producing a digital image from said video signal.

23. The system of claim 22 wherein each pixel of said digital image contains information from no more than one third of the minimum size of any feature being captured on said IC.

24. The system of claim 23 wherein said microscope and camera mechanism is able to distinguish 500 individual pixels in both the X and Y directions.

25. In a computer system capable of receiving and processing video signals, a process for extracting design information from an integrated circuit (IC) comprising the steps of:

capturing an image of said IC by successively scanning each of a plurality of physical layers which comprise said IC utilizing a microscope and video camera;

storing said image in a memory within said computer system;

processing said image to generate a condensed and abstract representation of said IC, said abstract representation containing lists of physical features detected in said image and their relative positions, said physical features including the geometric shapes and dimensions of various components which comprise individual circuit elements of said IC, said processing step including the step of filtering said image to distinguish said physical features from background information;

recognizing said individual circuit elements present in said IC by comparing said abstract representation with a reference library of circuits stored in a similarly abstract form utilizing said computer system;

determining the connections between said circuit elements;

cataloguing said connections in the form of a netlist;

abstracting groups of said circuit elements and their associated connections into a logical representation indicative of the functionality of said circuit elements and their associated connections.

26. The process according to claim 25 wherein said memory comprises a magnetic disk drive recording system.

27. In a computer system capable of receiving and processing video signals, a process for extracting design information from an integrated circuit (IC) comprising the steps of:

(a) inputting a magnified image of one layer of said IC into said computer system by successively capturing tiled images of all of the various sections of said IC;

(b) processing said magnified image of said one layer to generate an abstract representation of said IC, said abstract representation including lists of features detected in said image and their relative positions, said lists providing a means by which individual circuit cells can be identified;

(c) repeating steps (a) and (b) until all layers necessary for circuit recognition have been captured;

(d) combining the abstract representations associated with each of said layers to form a single intermediate representation of said IC;

(e) utilizing a reference library of circuits stored in an intermediate representation within said computer system to recognize instances of said circuits on said IC;

(f) overlaying said recognized instances with schematic representations of said circuits;

(g) repeating steps (e) and (f) until all circuit elements on said IC and their associated connections have been processed;

(h) optionally overlaying the schematics of groups of connected circuit elements with a high level circuit representation indicative of the functionality of said connected elements; and

(i) outputting a schematic netlist of said IC.

28. The process according to claim 27 wherein said tiled images of said sections partially overlap one another to ensure complete image capture of said IC.

29. The process according to claim 28 wherein said lists of features include the dimensions and relative location of transistors, and the width, length and relative location of metal interconnects on said IC.

30. The process according to claim 28 wherein said one layer comprises the second metalization layer of said IC.

31. The process according to claim 30 wherein step (a) comprises the steps of:

mounting said IC on a motorized X-Y table such that the X-Y axes of said IC are roughly aligned with the X-Y axes of said table;

establishing a boundary about said IC by referencing first and second recognizable features located at opposite corners of said IC, said recognizable features being located in the same position on all of said layers;

capturing said magnified image of said one layer by successively capturing individual images of said section of said IC within said boundary by movement of said table along said X-Y axes.

32. The process according to claim 31 wherein step (b) comprises the steps of:

applying image processing/filtering algorithms to said tiled images to produce a corresponding set of contrast-enhanced images;

identifying said features of said contrast-enhanced images and generating said list therefrom;

building a composite image to generate said abstract representation of said one layer by matching said features at the edges of adjacent sections of said IC;

correlating said composite image with said contrast-enhanced images.

33. The process according to claim 32 wherein step (d) comprises the steps of:

aligning said abstract representation associated with each of said layers to said recognizable features; and

combining said abstract representation associated with each of said layers to form said single intermediate representation of said IC.

34. The process according to claim 33 further comprising the steps of:

creating a set of identification features for each of said circuit elements contained in said single intermediate representation by tagging a subset of said list of features which most often uniquely identify said circuit elements; and

calculating the relative distances between neighboring identification features.

35. The process according to claim 27 wherein step (e) comprises the steps, for each of said circuit elements to be recognized, of:

comparing said internal representation of each of said instances of said reference library circuits with said set of identification features associated with one of said circuit elements on said IC;

declaring a match when the correspondence between one of said circuit elements and one of said reference library circuits exceeds a predetermined threshold.