Manufacturing method for a power MISFET

• US 5,087,577 A
• Filed: 06/05/1991
• Issued: 02/11/1992
• Est. Priority Date: 06/05/1990
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Strack, Helmut
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Thomas, Tom
• Application Number:
  US07/710,588
• Time in Patent Office: 251 Days
• Field of Search: 437/29, 437/40, 437/41, 437/203, 437/228, 437/235, 148/DIG. 126, 357/23.4
• US Class Current: 438/273
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

A manufacturing method for a low-voltage power MISFET which utilizes three maskes (photosteps) is provided. In the first step, a polysilicon layer is structured and a cell field and edge zones are manufactured. An oxide layer is then applied, this being opened in the second photostep above the cells and the edge zones and between the edge and the cells. A metal layer is then applied, this being interrupted between the cells and the edge zones with the third photostep. Field plates and a channel stopper are thus produced.

Claims

1. A method for manufacturing a power MISFET with a semiconductor body which comprises a field of transistor cells as well as at least one field plate and at least one channel stopper, comprising the steps of:

covering the semiconductor body with a first oxide layer;

covering the first oxide layer with a polysilicon layer;

structuring the polysilicon layer with a first photostep;

producing the transistor cells and producing edge zones lying above one another for the channel stopper;

covering the semiconductor body with a second oxide layer;

with a second photostep, producing through holes in the second oxide layer in a region of the transistor cells and producing an opening for contact regions at the edge zones in the second oxide layer, and producing an annular depression which surrounds the transistor cells in the polysilicon layer between the transistor cells and the edge zones;

implanting dopants which have a conductivity type opposite that of the semiconductor body into the semiconductor body through the depression with a dose which is lower than a dose employed for the transistor cells and for the edge zones;

covering the semiconductor body with a metal layer; and

with a third photostep, completely interrupting the metal layer and the polysilicon layer in a region of the annular depression.

2. A method according to claim 1 wherein the semiconductor body is covered with a passivation layer following the step of interrupting the metal layer and the polysilicon layer.

3. A method for manufacturing a power MISFET with a semiconductor body which comprises a field of transistor cells as well as at least one field plate and at least one channel stopper, comprising the steps of:

covering the semiconductor body with a first oxide layer;

covering the first oxide layer with a polysilicon layer;

structuring the polysilicon layer with a first photostep;

producing the transistor cells and producing edge zones lying above one another for the channel stopper;

covering the semiconductor body with a second oxide layer;

with a second photostep, producing through holes in the second oxide layer in a region of the transistor cells and producing an opening for a contact region at the edge zones in the second oxide layer, and producing an annular depression which surrounds the transistor cells in the polysilicon layer between the transistor cells and the edge zones;

covering the semiconductor body with a metal layer;

with a third photostep, completely interrupting the metal layer and the polysilicon layer in a region of the annular depression; and

implanting dopants which have a conductivity type opposite that of the semiconductor body into the semiconductor body through the depression with a dose which is lower than a dose employed for the transistor cells and for the edge zones.

4. A method according to claim 3 wherein the semiconductor body is covered with a passivation layer after the step of implanting the dopants in the semiconductor body through the depression.

5. A method for manufacturing a power MISFET with a semiconductor body which comprises a field of transistor cells as well as at least one field plate and at least one channel stopper, comprising the steps of:

covering the semiconductor body with a first oxide layer;

covering the first oxide layer with a polysilicon layer;

structuring the polysilicon layer with a first photostep;

producing the transistor cells and producing edge zones for the channel stopper;

covering the semiconductor body with a second oxide layer;

with a second photostep, producing through holes in the second oxide layer in a region of the transistor cells and producing an opening for contact regions at the edge zones in the second oxide layer, and producing a depression which surrounds the transistor cells in the polysilicon layer;

implanting dopants which have a conductivity type opposite that of the semiconductor body into the semiconductor body through the depression;

covering the semiconductor body with a metal layer; and

with a third photostep, interrupting the metal layer and the polysilicon layer in a region of the depression.

6. A method for manufacturing a power MISFET with a semiconductor body which comprises a field of transistor cells as well as at least one field plate and at least one channel stopper, comprising the steps of:

covering the semiconductor body with a first oxide layer;

covering the first oxide layer with a polysilicon layer;

structuring the polysilicon layer with a first photostep;

producing the transistor cells and producing edge zones for the channel stopper;

covering the semiconductor body with a second oxide layer;

with a second photostep, producing through holes in the second oxide layer in a region of the transistor cells and producing an opening for a contact region at the edge zones in the second oxide layer, and producing a depression which surrounds the transistor cells in the polysilicon layer;

covering the semiconductor body with a metal layer;

with a third photostep, interrupting the metal layer and the polysilicon layer in a region of the depression; and

implanting dopants which have a conductivity type opposite that of the semiconductor body into the semiconductor body through the depression.