Process for fabricating a contactless floating gate memory array utilizing wordline trench vias

• US 5,087,584 A
• Filed: 04/30/1990
• Issued: 02/11/1992
• Est. Priority Date: 04/30/1990
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Trudel, Murray L., Wada, Glen N.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US07/516,161
• Time in Patent Office: 652 Days
• Field of Search: 437/43, 437/49, 437/195, 437/52, 437/44, 437/67, 437/69, 357/23.5, 148/DIG. 50
• US Class Current: 438/262
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: Y10S 148/05 Etch and refill

Abstract

A process for fabricating ultra-high density (e.g., 64Mbit) contactless EPROMs and/or flash EPROMs in a silicon substrate is described. Spaced-apart island members are formed of poly 2/ dielectric/poly 1 layers over gate oxide regions. Each island member is associated with one of the cells within the array, and is separated from each other by trenches extending down to either the field oxide or substrate regions. Elongated, parallel, spaced-apart source/drain regions are formed on adjacent sides of the channel regions by ion implantation. The trenches are then filled with an insulating material and a plurality of wordlines patterned across the array. Each wordline makes electrical contact to the control gate members associated with the single row of cells within the array.

Claims

1. A process for fabricating an array of floating gate memory cells in a p-type silicon substrate comprising the steps of:

forming field oxide regions in said substrate which define the channel regions of said cells;

forming gate oxide regions over said substrate between said field oxide regions;

depositing a first polysilicon layer over said substrate;

forming a dielectric layer over said polysilicon layer;

depositing a second polysilicon layer over said dielectric layer;

etching said second polysilicon, said dielectric and said first polysilicon layers to form a plurality of island members over said gate oxide regions, each of said island members comprising said dielectric layer sandwiched between said first and said second polysilicon layers, and each of said island members being associated with one of said cells in said array, said island members being separated from each other by trenches wherein said first polysilicon layer comprises the floating gate members and said second polysilicon layer comprises the control gate members of said cells;

introducing n-type dopants into said substrate to form spaced-apart source/drain regions adjacent to said channel regions of said cells;

filling said trenches with an insulating material by;

depositing an insulative layer over said substrate to fill said trenches and cover said island members;

masking said insulative layer;

etching said insulative layer to form a plurality of elongated, parallel, spaced-apart openings in said insulative layer over said control gate members; and

forming a plurality of wordlines across said array, said wordlines making electrical contact to said control gate members associated with a row of said cells.

2. The process according to claim 1 wherein the material for said wordlines is selected from the group consisting essentially of aluminum, polysilicon and tungsten.

3. The process according to claim 2 wherein said dielectric layer comprises an oxide/nitride/oxide composite.

4. The process according to claim 3 wherein said gate oxide is approximately 115 Å

thick.

5. The process according to claim 4 wherein said dopants comprise arsenic.

6. The process according to claim 5 wherein said wordlines comprise tungsten.

7. The process according to claim 1 further comprising the step of forming a spacer oxide along the side wall portions of said island members following the formation of said island members.

8. The process according to claim 1 wherein said etching step comprises the steps of:

etching said second polysilicon, said dielectric and said first polysilicon layers to form a plurality of elongated, parallel, spaced-apart stacks extending across said array in a first direction;

forming masking members patterned over said stacks in a second direction generally perpendicular to said first direction;

etching the exposed portions of said stacks thereby forming said island members and said trenches; and

etching the exposed portions of said field oxide regions.

9. The process according to claim 8 wherein said introducing step is performed prior to the removal of said masking members.

10. A process for fabricating an array of floating gate memory cells in a p-type silicon substrate comprising the steps of:

forming elongated field oxide regions in said substrate extending across said array in a first direction, said field oxide regions defining the channel regions of said cells;

forming elongated gate oxide regions over said substrate between said field oxide regions, said gate oxide regions also extending across said array in said first direction;

depositing a first polysilicon layer over said substrate;

forming a dielectric layer over said first polysilicon layer;

depositing a second polysilicon layer over said second dielectric layer;

masking said second polysilicon layer;

etching said second polysilicon layer, said dielectric and said first polysilicon layer to form a plurality of spaced-apart, elongated stacks extending across said substrate in said first direction, each of said stacks overlying said gate oxide regions and comprising said dielectric layer sandwiched between said first and second polysilicon layers;

masking said stacks;

etching said stacks in a second direction generally perpendicular to said first direction to form a plurality of island members separated by trenches, each of said island members being associated with one of sai cells in said array wherein said first polysilicon layer comprises the floating gate members and said second polysilicon layer comprises the control gate members of said cells;

implanting n-type dopants into said substrate to form elongated, parallel, spaced-apart source/drain regions adjacent to said channel regions of said cells;

filling said trenches with an insulating material by;

depositing an insulative layer over said substrate to fill said trenches and cover said island members rendering said substrate substantially planar;

masking said insulative layer;

etching said insulative layer in said first direction to form a plurality of elongated, parallel, spaced-apart openings in said insulative layer over said control gate members;

stopping said etching of said insulative layer after the top surface of said control gate members has been exposed; and

forming a plurality of wordlines across said array, each of said wordlines making electrical contact to said control gate members associated with a row of said cells.

11. The process according to claim 10 wherein said source/drain regions extend across said array in said second direction.

12. The process according to claim 11 wherein said dielectric layer comprises an oxide/nitride/oxide composite.

13. The process according to claim 12 wherein the material for said wordlines is selected from the group consisting essentially of aluminum, polysilicon and tungsten.

14. The process according to claim 13 wherein said implanting step comprising the steps of:

implanting a first ion species into said source and drain regions; and

implanting a second ion species into said source region such that said source region is deeper and more graded when compared to said drain region.

15. The process according to claim 14 wherein said first ion species comprises arsenic and said second ion species comprises phosphorous.

16. The process according to claim 15 wherein said gate oxide is approximately 115 Å

thick.

17. The process according to claim 16 wherein said wordlines extend across said array in said first direction.

18. The process according to claim 17 wherein said wordlines comprises tungsten.

19. The process according to claim 10 further comprising the step of forming a spacer oxide along the side wall portions of said island members following the formation of said island members.

20. The process according to claim 19 further comprising, prior to said implanting step, the step of etching the exposed portions of said field oxide regions down to said substrate.

21. The process according to claim 20 further comprising, immediately after said implanting step, the step of reoxidizing said substrate.

22. A process for fabricating an array of floating gate memory cells on a silicon substrate of a first conductivity type comprising the steps of:

forming an oxide on said substrate;

forming elongated field oxide regions in said substrate in a first direction thereby defining the channel regions of said cells;

removing said oxide;

thermally growing elongated gate oxide regions over said substrate between said field oxide regions, said gate oxide regions extending across said array in said first direction;

depositing a first polysilicon layer over said substrate;

forming an interpoly dielectric layer comprising an oxide/nitride/oxide composite over said first polysilicon layer;

depositing a second polysilicon layer over said interpoly dielectric layer;

depositing tungsten silicide layer over said second polysilicon layer;

masking said tungsten silicide layer;

etching said tungsten silicide layer, said second polysilicon layer, said dielectric in said first polysilicon layer to form a plurality of elongated, parallel, spaced-apart stacks extending across said substrate in said first direction, each of said stacks being formed over said gate oxide regions and comprising, from top to bottom, said tungsten silicide, said second polysilicon, said interpoly dielectric, and said first polysilicon layers;

masking said stacks;

etching said stacks in a second direction generally perpendicular to said first direction to form a plurality of island members separated by trenches, each of said island members being associated with one of said cells in said array wherein said first polysilicon layer comprises the floating gate members and said tungsten silicide and said second polysilicon layers comprise the control gate members of said cells;

etching said field oxide regions in said second direction;

implanting ions into said substrate to form elongated, parallel, spaced-apart, source/drain regions of a second conductivity type extending across said array in said second direction adjacent to said channel regions of said cells;

depositing an insulative layer over said substrate to fill said trenches and cover said island members in a substantially planar fashion;

masking said insulative layer;

anisotropically etching said insulative layer along said first direction to form a plurality of elongated, parallel, spaced-apart openings in said insulative layer over said control gate members;

stopping said etching of said insulative layer after the top surface of said control gate members has been exposed and before the sides of said interpoly dielectric have been exposed;

forming a plurality of wordlines across said array in said first direction, each of said wordlines making electrical contact to said control gate members associated with a row of said cells.

23. The process according to claim 22 wherein said first conductivity type is p-type and said second conductivity type is n-type.

24. The process according to claim 23 further comprising the step of performing a boron field implant prior to the formation of said field oxide regions.

25. The process according to claim 22 wherein the material for said wordlines is selected from the group consisting essentially of aluminum, polysilicon and titanium.

26. The process according to claim 25 further comprising the step of reoxidizing said substrate immediately following said implanting step.

27. The process according to claim 26 wherein said implanting step comprising the steps of:

implanting a first ion species into said source and drain regions; and

implanting a second ion species into said source region such that said source region is deeper and more graded when compared to said drain region.

28. The process according to claim 27 wherein said gate oxide is approximately 115 Å

thick.

29. The process according to claim 22 wherein said wordlines comprise tungsten or tungsten silicide.

30. The process according to claim 29 further comprising the step of forming a spacer oxide along the side wall portions of said island members following the formation of said island members.