Integrated circuit having processor coupled by common bus to programmable read only memory for processor operation and processor uncoupled from common bus when programming read only memory from external device

• US 5,088,023 A
• Filed: 05/30/1989
• Issued: 02/11/1992
• Est. Priority Date: 03/23/1984
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakamura, Hideo, Sawase, Terumi
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): ELLIS, RICHARD L
• Application Number:
  US07/358,523
• Time in Patent Office: 987 Days
• Field of Search: 364/200, 364/900, 371/15, 371/21
• US Class Current: 711/103
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 15/786 using a single memory module

Abstract

The present invention discloses an integrated circuit having a data bus, an address bus, a processor and a memory each connected to the data bus and the address bus, a first transmitter for transmitting data inputted to a data terminal to the data bus, a second transmitter for transmitting data on the data bus to the data terminal, a third transmitter for transmitting an address inputted to an address terminal to the address bus, and signal generate means for generating signals to set the respective outputs from the first and third transmitters to the high impedance in response to a memory read request supplied from the processor, for generating signals to set the respective outputs from a data output of memory module to transmit data from the memory to the data bus, the first transmitter, and the third transmitter to the high impedance in response to a memory write request, for generating signals to set the respective outputs from a data output of processor module and an address output of processor module to output data and an address from the processor to the data bus and the address bus, respectively to the high impedance in response to a memory read request from an external device, and for generating signals to set the respective outputs from the data output of processor module and the address output of processor module in response to a memory write request from an external device, the integrated circuit further including a fourth transmitter for transmitting an address on the address bus to the address terminal, wherein the signal generate means generates signals to set the outputs from the first and third transmitters to the high impedance in response to an external memory read request supplied from the processor, sets the respective outputs from the data output of memory module, the first transmitter, and the third transmitter to the high impedance in response to an external memory write request supplied from the processor, and responds to the read or write request from the external device in preference to the read or write request from the processor.

Claims

1. A microcomputer implemented as an LSI and having a CPU block and an electrically programmable read only memory which is programmable by an external device, said microcomputer comprising:

bus means for transferring data and address signals;

a CPU block for processing data according to instructions;

a memory block for storing instructions, said memory block having at least said electrically programmable memory;

first terminal means for connecting to an external device;

first gate means for controlling transfer of data and address signals from said bus means to said first terminal means;

second gate means for controlling transfer of data and address signals from said first terminal means to said bus means;

first transfer means for transferring data from said bus means to said CPU block;

second transfer means for transferring data and address signals from said bus means to said memory block;

third gate means for controlling transfer of data and address signals from said CPU block to said bus means;

fourth gate means for controlling transfer of data from said memory block to said bus means;

second terminal means for receiving an external signal for effecting writing of data in said electrically programmable memory means from said external device; and

control means responsive to control signals received from said CPU block for controlling said first through fourth gate means to provide for transfer of instructions from said memory block to said CPU block for effecting processing of data by said CPU block, and responsive to said external signal received from said second terminal means for forcibly controlling at least said third gate means to cut-off transfer of data and address signals from said CPU block to said bus means so as to provide for transfer of data and address signals from said first terminal means to said electrically programmable memory via said bus means to effect programming thereof independent of said CPU block.

2. A microcomputer according to claim 1, wherein said control means includes means responsive to said signals received from said second terminal means for blocking said control signals from said CPU block.

3. A microcomputer according to claim 1, wherein said control means is implemented as a programmable logic array.

4. A microcomputer according to claim 1, wherein said electrically programmable read only memory is an ultra-violet ray erasable nonvolatile memory.

5. A microcomputer implemented as an LSI device comprising:

a CPU block;

a memory block for storing instructions at selected addresses of said memory block and including an electrically programmable memory which is programmable by an external device independently of said CPU block;

an address bus having a plurality of address lines for transferring addresses from said CPU block to said memory block;

a data bus having a plurality of data lines for transferring data between said CPU block and said memory block;

first terminal means for coupling said address bus to said external device;

second terminal means for coupling said data bus to said external device;

coupling means for selectively coupling said data bus and said address bus to said CPU block; and

control means coupled to said coupling means and an external terminal for controlling said coupling means to uncouple said CPU block from said address bus and said data bus when an external access mode signal is received via said external terminal to effect programming of said electrically programmable memory by said external device independently of said CPU block via said first terminal means and said second terminal means;

wherein programming of said electrically programmable memory from said external device can be performed via said address bus and said data bus.

6. A microcomputer according to claim 5, wherein said external device is an EPROM programmer which generates addresses and corresponding data.

7. A microcomputer according to claim 5, wherein said external terminal is coupled to said control means for supplying to said control means a mode control signal, said CPU block is coupled to said control means for supplying to said control means a access control signal, and said control means blocks said access control signal from said CPU block when said mode control signal specifies an external access mode.

8. A microcomputer according to claim 7, wherein said control means enables said CPU block to access said memory block in accordance with said access control signal when said mode control signal specifies an internal access mode.

9. A microcomputer according to claim 5, wherein said control means includes control signal generating means which is implemented as a programmable logic array.

10. A microcomputer according to claim 5, wherein said electrically programmable memory is an ultra-violet ray erasable nonvolatile read only memory.