Memory device having common data lines for reading and writing

• US 5,088,062 A
• Filed: 03/15/1990
• Issued: 02/11/1992
• Est. Priority Date: 03/15/1989
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Corporation (Panasonic Holdings Corporation)
• Inventors: Shikata, Michiharu
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/493,683
• Time in Patent Office: 698 Days
• Field of Search: 365/233, 365/233.5, 365/189.05, 365/189.02, 365/238.5, 365/189.04, 365/230.02
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/1033 using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/109 Control signal input circuits

Abstract

A semiconductor memory device includes a memory cell array having plural memory cells disposed in an array. A sense amplifier is provided for selecting a plurality of memory cells from among the plural memory cells of the memory cell array. Data lines are provided coupled to the sense amplifier. Each of the data lines is for transmitting write data to and read data from the memory cell array. A read data latch circuit is provided having a plurality of latch circuits respectively coupled to the data lines. Additionally, a write data latch circuit is provided having a plurality of buffer circuits respectively coupled to the data lines. Thus, a common transmitting path is provided for both inputting data and outputting data from the memory cell array. Upon carrying out a write operation for writing of the write data into the memory cell array, the write data is stored in both the read data latch circuit and the write data latch circuit at the same time.

Claims

1. A semiconductor memory device comprising:

a memory cell array having plural memory cells disposed in an array;

selecting means for selecting a plurality of memory cells from among said plural memory cells of said memory cell array;

a plurality of data lines coupled to said selecting means, each of said plurality of data lines for transmitting write data to and read data from said memory cell array;

a read data latch means, having a plurality of latch circuits respectively coupled to said plurality of data lines, for temporarily storing data therein; and

,

a write data latch means, having a plurality of buffer circuits respectively coupled to said plurality of data lines, for temporarily storing data therein;

wherein, upon carrying out a write operation for writing of the write data into said memory cell array, the write data is stored in both said read data latch means and said write data latch means at the same time.

2. A semiconductor memory device as recited in claim 1, further comprising means for transmitting in a batch operation the write data stored in said write data latch means to said memory cell array.

3. A semiconductor memory device as recited in claim 2, further comprising means for storing the read data in said read data latch means and for sequentially reading the read data stored in said read data latch means.

4. A semiconductor memory device as recited in claim 2, further comprising a write history detecting means for storing write history information indicative of a write operation of said write data latch means.

5. A semiconductor memory device as recited in claim 4, further comprising means for generating a write control signal responsive to the write history information stored in said write history detecting means, wherein the batch operation is carried out responsive to the write control signal.

6. A semiconductor memory device as recited in claim 5, wherein said write history detecting means includes a single stage of latch circuits.

7. A semiconductor memory device as recited in claim 6, further comprising a selector circuit coupled to said plurality of data lines.

8. A semiconductor memory device as recited in claim 4, wherein said write history detecting means includes a single stage of latch circuits.

9. A semiconductor memory device as recited in claim 5, further comprising means for transmitting data from each of said plurality of latch circuits of said read data latch means to an associated one of said plurality of buffer circuits of said write data latch means in which corresponding data have not been stored.

10. A semiconductor memory device as recited in claim 9, further comprising a selector circuit coupled to said plurality of data lines.

11. A semiconductor memory device as recited in claim 2, further comprising a selector circuit coupled to said plurality of data lines.

12. A semiconductor memory device as recited in claim 2, further comprising means for transmitting data from each of said plurality of latch circuits of said read data latch means to an associated one of said plurality of buffer circuits of said write data latch means in which corresponding data have not been stored.

13. A semiconductor memory device as recited in claim 1, further comprising means for storing the read data in said read data latch means and for sequentially reading the read data stored in said read data latch means.

14. A semiconductor memory device as recited in claim 1, further comprising a write history detecting means for storing write history information indicative of a write operation of said write data latch means.

15. A semiconductor memory device as recited in claim 14, wherein said write history detecting means includes a single stage of latch circuits.

16. A semiconductor memory device as recited in claim 14, further comprising means for transmitting data from each of said plurality of latch circuits of said read data latch means to an associated one of said plurality of buffer circuits of said write data latch means in which corresponding data have not been stored.

17. A semiconductor memory device as recited in claim 1, further comprising means for transmitting data from each of said plurality of latch circuits of said read data latch means to an associated one of said plurality of buffer circuits of said write data latch means in which corresponding data have not been stored.

18. A semiconductor memory device as recited in claim 1, wherein a number of said plurality of buffer circuits and a number of said plurality of latch circuits is the same and is one of four and eight.

19. A semiconductor memory device as recited in claim 1, wherein a number of said plurality of buffer circuits and a number of said plurality of latch circuits is the same and corresponds to a number of bits in a row unit of a memory address space of said memory cell array.

20. A semiconductor memory device as recited in claim 1, further comprising a selector circuit coupled to said plurality of data lines.