Mask surrogate semiconductor process employing dopant-opaque region

• US 5,089,434 A
• Filed: 01/22/1990
• Issued: 02/18/1992
• Est. Priority Date: 03/21/1986
• Status: Expired due to Term

• Current Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Original Assignee: Advanced Power Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Hollinger, Theodore G.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Thomas, Tom
• Application Number:
  US07/467,947
• Time in Patent Office: 757 Days
• Field of Search: 437/29, 437/31, 437/40, 437/41, 437/228, 437/233, 437/235, 357/23.4
• US Class Current: 438/274
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structure formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O₂ -SF₆ plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.

Claims

1. A method, employing no more than one independent mask, of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, the method comprising:

`forming over the gate oxide layer a dopant protective layer;

creating a mask-surrogate pattern-definer having a defined outline characteristic in the protective layer;

exposing a portion of the upper surface of the substrate within a region bounded by the defined outline characteristic;

performing a first coping step to introduce dopant into said exposed upper surface portion of the substrate so as to form a first region of a first conductivity type, opposite a second conductivity type which is the conductivity type of a second region in said substrate, said first region including said exposed under surface of the substrate and extending to a location under peripheral edges of the protective layer providing the defined outline characteristic, said first region being wholly contained in said second region; and

after the first doping step, forming a trench in the exposed upper surface of the substrate, the trench being formed to a trench depth greater than a depth of the first region but less than a depth of the second region, and being formed of a width less than a width of the first region such that separated regions of the first conductivity type are provided at sidewalls of the trench, the separated regions constituting source regions of the MOS semiconductor device,

the trench sidewalls being formed to protrude laterally toward one another within the trench so that a portion of the silicon substrate containing the first region of said first conductivity type is vertically exposed along the trench sidewalls.

2. A method according to claim 1, wherein the protective layer is a dopant-opaque layer.

3. A method according to claim 1, including a further step of depositing a conductive material layer, after forming the trench, having a first portion in the trench in contact with the separated regions and a second portion on the oxide layer, so as to provide electrical contact to the source regions and to form a gate conductive layer of the MOS semiconductor device.

4. A method according to claim 3, wherein the conductive material layer is deposited such that said first portion, when deposited, is separated vertically from said first portion, the first and second portions being deposited at the same time.

5. A method according to claim 1, wherein the second region is formed in said substrate by performing a second doping step, prior to said first doping step, into the exposed upper surface of the substrate, so as to form the second region to extend to a location under the protective layer providing the defined outline characteristic.

6. A method according to claim 5, wherein the second region is formed to extend a distance under the protective layer providing the defined outline characteristic that is 60%-80% of a depth of the second region from the upper surface of the substrate.

7. A method employing no more than one independent mask of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising:

forming over the gate oxide layer a dopant protective layer;

creating a mask-surrogate pattern-definer having a defined outline characteristic in the protective layer;

exposing a portion of the upper surface of the substrate within a boundary determined by the defined outline characteristic;

forming a trench in the exposed upper surface portion of the substrate, the trench having a base and opposite sidewalls in which a lower substrate surface is exposed, the sidewalls being undercut beneath the gate oxide layer;

and simultaneously depositing a gate conductive layer on the oxide layer and a source conductive layer on the lower surface of the substrate, the gate and source conductive layers each conforming to the boundary defined by the defined outline characteristic;

the trench being formed to a trench depth and the source conductive layer to a thickness mutually arranged, spacing the source conductive layer below the oxide layer so as to contact the substrate along the sidewalls of the trench and so that the gate and source conductive layers are electrically separated vertically along said boundary.

8. A method according to claim 7 in which the dopant protective layer is polysilicon.

9. A method according to claim 7 including ion implanting a dopant into the exposed portion of the substrate prior to forming the trench so that the trench divides the doped substrate portion into separate source regions extending along each trench sidewall.

10. A method employing no more than one independent mask of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising:

forming over the gate oxide layer a dopant protective layer;

creating a mark-surrogate pattern-definer having a defined outline characteristic in the protective layer;

exposing a portion of the upper surface of the substrate within a boundary determined by the defined outline characteristic;

forming a trench in the exposed upper surface portion of the substrate, the trench having a base and opposite sidewalls in which a lower substrate surface is exposed and the trench sidewalls are inclined toward one another in a depthwise direction;

and simultaneously depositing a gate conductive layer on the oxide layer and a source conductive layer on the lower surface of the substrate, the gate and source conductive layers each conforming to the boundary defined by the defined outline characteristic;

the trench being formed to a trench depth and the source conductive layer to a thickness mutually arranged, spacing the source conductive layer below the oxide layer so as to contact the substrate along the sidewalls of the trench and so that the gate and source conductive layers are electrically separated vertically along said boundary.

11. A method according to claim 10 in which the sidewalls are undercut beneath the gate oxide layer.

12. A method according to claim 10 in which the dopant protective layer is polysilicon and the step of forming the trench includes reducing the thickness of the polysilicon layer.

13. A method employing no more than one independent mask of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising:

forming over the gate oxide layer a polysilicon dopant protective layer;

creating a mask-surrogate pattern-definer having a defined outline characteristic in the protective layer;

exposing a portion of the upper surface of the substrate within a boundary determined by the defined outline characteristic;

forming a trench in the exposed upper surface portion of the substrate, the trench having a base and opposite sidewalls in which a lower substrate surface is exposed;

reducing the thickness of the polysilicon layer; and

simultaneously depositing a gate conductive layer on the oxide layer and a source conductive layer on the lower surface of the substrate, the gate and source conductive layers each conforming to the boundary defined by the defined outline characteristic;

the trench being formed to a trench depth and the source conductive layer to a thickness mutually arranged, spacing the source conductive layer below the oxide layer so as to contact the substrate along the sidewalls of the trench and so that the gate and source conductive layers are electrically separated vertically along said boundary.

14. A method employing no more than one independent mask of producing an MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising:

forming over the gate oxide layer a dopant protective layer;

creating a mask-surrogate pattern-definer having a defined outline characteristic in the protective layer;

exposing a portion of the upper surface of the substrate within a boundary determined by the defined outline characteristic;

forming a trench in the exposed upper surface portion of the substrate, the trench having a base and opposite sidewalls in which a lower substrate surface is exposed;

and simultaneously depositing a gate conductive layer on the oxide layer and a source conductive layer on the lower surface of the substrate, the gate and source conductive layers each conforming to the boundary defined by the defined outline characteristic;

the trench being formed to a trench depth and the source conductive layer to a thickness mutually arranged, spacing the source conductive layer below the oxide layer so as to contact the substrate along the sidewalls of the trench and so that the gate and source conductive layers are electrically separated vertically along said boundary,

the trench sidewalls being formed to protrude laterally toward one another within the trench so that a portion of the silicon substrate containing a first region of a first conductivity type is vertically exposed along each of the trench sidewalls.