Interrogation signal processor for air traffic control communications

• US 5,089,822 A
• Filed: 02/13/1990
• Issued: 02/18/1992
• Est. Priority Date: 02/13/1990
• Status: Expired due to Fees

• Current Assignee: Avion Systems, Inc.
• Original Assignee: Avion Systems, Inc.
• Inventors: Abaunza, John T., Merritt, Scott A.
• Primary Examiner(s): Sotomayor, John B.
• Application Number:
  US07/479,265
• Time in Patent Office: 735 Days
• Field of Search: 342/30, 342/31, 342/32, 342/36, 342/37, 342/38, 342/40, 342/35, 342/42, 329/304, 329/345, 340/825.58, 375/84
• US Class Current: 342/30
• CPC Class Codes: G01S 13/765 with exchange of information between interrogator and responder
• CPC Class Codes: G01S 13/767 Responders; Transponders teaching or practice apparatus for gun-aiming or gun-laying using reflecting targets or active targets F41G3/26
• CPC Class Codes: H04L 27/2331 wherein the received signal is demodulated using one or more delayed versions of itself

Abstract

The present invention is directed to a Mode S uplink or interrogation signal demodulation system which can quickly recognize the Mode S signal and also filter out of noise present in the Mode S uplink or interrogation signal, thereby reducing the bit error rate. To realize this goal the present invention includes a digital differential phase-shift keyed demodulator to demodulate the differential phase-shift keyed data, thereby reducing the time needed to acquire the Mode S uplink or interrogation signal. This digital demodulator also reduces the noise present in the Mode S uplink or interrogation signal and provides an integrated system which is small in structure that can be easily implemented in an aircraft. This Mode S system also includes a preamble and sync phase reversal detection circuit to recognize if the transmitted signal is a Mode S signal. This signal also utilizes Mode A and Mode C detection devices to make the system compatible with present communication systems.

Claims

1. A digital Mode S Interrogation Signal Processor for implementation in either a Mode S transponder or air collision avoidance system, comprising:

Mode S preamble detector means for detecting a Mode S preamble of a transmitted signal and for generating a preamble detection signal;

phase-shift reversal detection means, in response to said preamble detection signal, for detecting a phase shift reversal in the transmitted signal and for generating a Mode S verification signal; and

said phase-shift reversal detection means determining that the transmitted signal is a Mode S signal when generating said Mode S verification signal;

digital differential phase-shift keyed demodulating means, in response to said Mode S verification signal, or digitally demodulating said Mode S signal to obtain useful information for air collision avoidance.

2. The digital Mode S Interrogation Signal Processor as claimed in claim 1, wherein said digital differential phase-shift keyed demodulating means comprises:

splitter means for splitting said Mode S signal into a quadrature signal and an in-phase signal, said quadrature signal being odd samples of said Mode S signal and said in-phase signal being even samples of said Mode S signal;

digital Hilbert transformation means, operatively connected to said splitter means, for performing a Hilbert transformation upon said quadrature signal and said in-phase signal to produce transformed signals;

delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle;

multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal;

summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; and

threshold means, operatively connected to said summer means, for determining a polarity of the sum produced by said summer means.

3. The digital Mode S Interrogation Signal Processor as claimed in claim 2, wherein said digital Hilbert transform means comprises:

Hilbert delay means, operatively connected to said splitter means, for delaying said quadrature signal and said in-phase signal by one clock cycle;

first subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and

second subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

4. The digital Mode S Interrogation Signal Processor as claimed in claim 2, wherein said threshold means produce data having a logic "1" when said polarity is positive and a logic "0" when said polarity is negative.

5. The digital Mode S Interrogation Signal Processor as claimed in claim 1, further comprising:

clock means, operatively connected to said phase shift reversal detector means and said digital differential phase shift keyed demodulator means, for producing a clock signal for said digital differential phase shift keyed demodulator in response to the detected phase shift reversal.

6. The digital Mode S Interrogation Signal Processor as claimed in claim 5, wherein said clock means produces a clock signal having a frequency of 16 MHz during a digital demodulation process.

7. The digital Mode S Interrogation Signal Processor as claimed in claim 1, wherein said Mode S preamble detector comprises:

comparator means, for comparing a voltage level of the transmitted Mode S signal with a reference threshold level to produce a pulse when said voltage level exceeds said reference threshold level; and

correlator means, operatively connected to said comparator means, for determining if said comparator means has produced two pulses and if said two pulses are separated by predetermined time gap;

said correlator means, producing preamble detection signal when said two pulses are present and are separated by said predetermined time gap.

8. The digital Mode S Interrogation Signal Processor as claimed in claim 7, wherein said reference threshold level is programmable.

9. The digital Mode S Interrogation Signal Processor as claimed in claim 4, further comprising:

computer means, operatively connected to said threshold means, for receiving serially said data produced by said threshold means and for using said data to avoid collisions with other moving objects.

10. The digital Mode S Interrogation Signal Processor as claimed in claim 1, further comprising:

Mode C means for processing and identifying a Mode C signal.

11. The digital Mode S Interrogation Signal Processor as claimed in claim 1, further comprising:

Mode A means for processing and identifying a Mode A signal.

12. The digital Mode S Interrogation Signal Processor as claimed in claim 2, wherein said multiplying means comprises:

first multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal;

second multiplying means, operatively connected to said delay means, for multiplying the delayed transformed in-phase signal with a current in-phase signal; and

weighting means, operatively connected to said summer means, said first and said second multiplying means, for arithmatically weighing the products from said first and second multiplying means such that middle samples of the transmitted signal are given greater weight, thereby avoiding interference at either edge of a passband of said Mode S signal.

13. The digital Mode S Interrogation Signal Processor as claimed in claim 12, wherein eight samples of the transmitted signal produce one bit of data.

14. The digital Mode S Interrogation Signal Processor as claimed in claim 1, wherein said digital differential phase-shift keyed demodulating means comprises:

splitter means for splitting said Mode S signal into a quadrature signal and an in-phase signal, said quadrature signal being odd samples of said Mode S signal and said in-phase signal being even samples of said Mode S signal;

digital Hilbert transformation means, operatively connected to said splitter means, for performing a Hilbert transformation upon said quadrature signal and said in-phase signal to produce transformed signals;

delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle;

multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal;

weighting means, operatively connected to said multiplying means, for arithmatically weighing the products from said multiplying means such that middle samples of the transmitted signal are given greater weight;

first summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means;

second summer means, operatively connected to said weighting means, for summing the weighted products produced by said weighting means;

switch means, operatively connected to said first and second summer means, for selecting a sum from either said first or second summer means in accordance with a type of noise and interference present in the transmitted signal; and

threshold means, operatively connected to said switch means, for determining a polarity of the selected sum from said switch means.

15. The digital Mode S Interrogation Signal Processor as claimed in claim 14, wherein eight samples of the transmitted signal produce one bit of data.

16. A Mode S Interrogation Signal Processor for collision avoidance system, comprising:

Mode S signal detector means for determining if a received signal is a Mode S signal;

splitter means, operatively connected to said Mode S signal detector means, for splitting a transmitted Mode S signal into a quadrature signal and an in-phase signal, said quadrature signal being odd-samples of said transmitted Mode S signal and said in-phase signal being even samples of said transmitted Mode S. signal;

digital Hilbert transformation means, operatively connected to said splitter means, for performing a Hilbert transformation upon said quadrature signal and said in-phase signal to produce transformed signals;

delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle;

multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal;

summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; and

threshold means, operatively connected to said summer means, for determining a polarity of the sum produced by said summer means.

17. The digital Mode S Interrogation Signal Processor as claimed in claim 16, wherein said threshold means produce data having a logic "1" when said polarity is positive and a logic "0" when said polarity is negative.

18. The Mode S Interrogation Signal Processor as claimed in claim 16, wherein said digital Hilbert transform means comprises:

Hilbert delay means, operatively connected to said splitter means, for delaying said quadrature signal and said in-phase signal by one clock cycle;

first subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and

second subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

19. The Mode S Interrogation Signal Processor as claimed in claim 16, wherein said Mode S signal detector means comprises:

comparator means, for comparing a voltage level of the transmitted signal with a threshold level to produce a pulse when said voltage level exceeds said threshold level; and

correlator means, operatively connected to said comparator means, for determining if said comparator means has produced two pulses and if said two pulses are separated by predetermined time gap;

said correlator means, producing a preamble detector signal when said two pulses are present and are separated by said predetermined time gap, thereby indicating that a Mode S signal is being received.

20. The Mode S Interrogation Signal processor as claimed in claim 16, further comprising:

computer means, operatively connected to said threshold means, for receiving serially said data produced by said threshold means and for using said data to avoid collisions with other moving objects.

21. The Mode S Interrogation Signal Processor as claimed in claim 16, further comprising:

Mode C means for processing and identifying a Mode C signal.

22. The Mode S Interrogation Signal Processor as claimed in claim 16, further comprising:

Mode A means for processing and identifying a Mode A signal.

23. The Mode S Interrogation Signal Processor as claimed in claim 16, wherein said multiplying means comprises:

first multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal;

second multiplying means, operatively connected to said delay means, for multiplying the delayed transformed in-phase signal with a current in-phase signal; and

weighting means, operatively connected to said summer means, said first multiplying means and said second multiplying means, for arithmatically weighing the products from said first and second multiplying means such that middle samples of the transmitted signal are given greater weight, thereby avoiding interference at either edge of a passband of said Mode S signal.

24. The digital Mode S Interrogation Signal Processor as claimed in claim 23, wherein eight samples of the said Mode S signal produce one bit of data.

25. A Mode S Interrogation Signal Processor for collision avoidance system, comprising:

splitter means, operatively connected to said Mode S signal detector means, for splitting a transmitted Mode S signal into a quadrature signal and an in-phase signal, said quadrature signal being odd-samples of said Mode S signal and said in-phase signal being even samples of said Mode S signal;

digital Hilbert transformation means, operatively connected to said splitter means, for performing a Hilbert transformation upon said quadrature signal and said in-phase signal to produce transformed signals;

delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle;

multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal;

weighting means, operatively connected to said multiplying means, for arithmatically weighing the products from said multiplying means such that middle samples of the transmitted signal are given greater weight;

first summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means;

second summer means, operatively connected to said weighting means, for summing the weighted products produced by said weighting means;

switch means, operatively connected to said first and second summer means, for selecting a sum from either said first or second summer means in accordance with a type of noise and interference present in the transmitted signal; and

threshold means, operatively connected to said switch means, for determining a polarity of the selected sum from said switch means.

26. The digital Mode S Interrogation Signal Processor as claimed in claim 25, wherein eight samples of the transmitted signal produce one bit of data.

27. The Mode S Interrogation Signal Processor as claimed in claim 25, wherein said digital Hilbert transform means comprises:

Hilbert delay means, operatively connected to said splitter means, for delaying said quadrature signal and said in-phase signal by one clock cycle;

first subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and

second subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

28. The Mode S Interrogation Signal Processor as claimed in claim 25, wherein said Mode S signal detector means comprises:

comparator means, for comparing a voltage level of the transmitted signal with a threshold level to produce a pulse when said voltage level exceeds said threshold level; and

correlator means, operatively connected to said comparator means, for determining if said comparator means has produced two pulses and if said two pulses are separated by predetermined time gap;

said correlator means, producing a preamble detection signal when said two pulses are present and are separated by said predetermined time gap, thereby indicating that a Mode S signal is being received.

29. The Mode S Interrogation Signal Processor as claimed in claim 25, further comprising:

computer means, operatively connected to said threshold means, for receiving serially said data produced by said threshold means and for using said data to avoid collisions with other moving objects.

30. The Mode S Interrogation Signal Processor as claimed in claim 25, further comprising:

Mode C means for processing and identifying a Mode C signal.

31. The Mode S Interrogation Signal Processor as claimed in claim 25, further comprising:

Mode A means for processing and identifying a Mode A signal.

32. The Mode S Interrogation Signal Processor as claimed in claim 28, wherein said threshold level is programmable.

33. A digital Mode S uplink demodulator for demodulating a received Mode S signal, comprising:

phase splitting means, for splitting the received Mode S signal into an in-phase signal and a quadrature signal;

digital Hilbert transformation means, operatively connected to said phase splitting means, for performing a Hilbert transformation upon said in-phase signal and said quadrature signal to produce transformed signals;

delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle;

multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal;

summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means; and

threshold means, operatively connected to said summer means, for determining a polarity of the sum produced by said summer means.

34. The digital Mode S uplink demodulator as claimed in claim 33, wherein said threshold means produce data having a logic "1" when said polarity is positive and a logic "0" when said polarity is negative.

35. The digital Mode S uplink demodulator as claimed in claim 33, wherein said digital Hilbert transform means comprises:

Hilbert delay means, operatively connected to said splitter means, for delaying said quadrature signal and said in-phase signal by one clock cycle;

first subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and

second subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

36. The digital Mode S uplink demodulator as claimed in claim 33, wherein said multiplying means comprises:

first multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal;

second multiplying means, operatively connected to said delay means, for multiplying the delayed transformed in-phase signal with a current in-phase signal; and

weighting means, operatively connected to said summer means, said first multiplying means and said second multiplying means, for arithmatically weighing the products from said first and second multiplying means such that middle samples of the transmitted signal are given greater weight, thereby avoiding interference at either edge of a passband of said Mode S signal.

37. The diqital Mode S uplink demodulator as olaimed in claim 36, wherein eight samples of the transmitted signal produce one bit of data.

38. A digital Mode S uplink demodulator for demodulating a received Mode S signal, comprising:

phase splitting means, for splitting the received Mode S signal into an in-phase signal and a quadrature signal;

digital Hilbert transformation means, operatively connected to said phase splitting means, for performing a Hilbert transformation upon said in-phase signal and said quadrature signal to produce transformed signals;

delay means, operatively connected to said digital Hilbert transformation means, for delaying the transformed quadrature and in-phase signals by one clock cycle;

multiplying means, operatively connected to said delay means, for multiplying the delayed transformed quadrature signal with a current transformed quadrature signal and for multiplying the delayed transformed in-phase signal by a current transformed in-phase signal;

weighting means, operatively connected to said multiplying means, for arithmatically weighing the products from said multiplying means such that middle samples are given greater weight;

first summer means, operatively connected to said multiplying means, for summing the products produced by said multiplying means;

second summer means, operatively connected to said weighting means, for summing the weighted products produced by said multiplying means;

switch means, operatively connected to said first and second summer means, for selecting a sum from either said first or second summer means in accordance with a type of noise or interference present in the transmitted signal; and

threshold means, operatively connected to said summer means, for determining a polarity of the sum produced by said summer means.

39. The digital Mode S uplink demodulator as claimed in claim 38, wherein said threshold means produce data having a logic "1" when said polarity is positive and a logic "0" when said polarity is negative.

40. The digital Mode S uplink demodulator as claimed in claim 38, wherein said digital Hilbert transform means comprises:

Hilbert delay means, operatively connected to said splitter means, for delaying said quadrature signal and said in-phase signal by one clock cycle;

first subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and

second subtractor means, operatively connected to said Hilbert delay means and said delay means, for subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

41. A method for digitally receiving a Mode S signal comprising the steps of:

(a) detecting a preamble of a transmitted Mode S signal;

(b) generating a preamble detection signal when said step (a) detects the preamble;

(c) detecting a phase shift reversal in the transmitted Mode S signal when the preamble detection signal is present;

(d) generating a phase reversal signal when said step (c) detects the phase shift reversal;

(e) splitting the transmitted Mode S signal into a quadrature signal and an in-phase signal;

(f) performing a digital Hilbert transformation upon the quadrature and in-phase signals;

(g) delaying the transformed quadrature and in-phase signals for one clock cycle;

(h) multiplying the delayed transformed quadrature signal by a current transformed quadrature signal;

(i) multiplying the delayed transformed in-phase signal by a current transformed in-phase signal;

(j) summing the products of said steps (i) and (h);

(k) determining a polarity of the sum of said step (j);

(l) producing data having a logic "1" when said step (k) determines the polarity to be positive; and

(m) producing data having a logic "0" when said step (k) determines the polarity to be negative.

42. The method as claimed in claim 41, wherein said step (a) comprises the steps of:

(n) comparing a voltage level of the transmitted Mode S signal with a threshold level;

(o) producing a pulse signal when said step (n) determines that the voltage level exceeds the threshold level;

(p) determining if said step (o) has produced two pulses which are separated by a predetermined time gap, thereby detecting a preamble of a Mode S signal when said step (o) has produced two pulses separated by the predetermined time gap.

43. The method as claimed in claim 42, wherein the threshold level is programmable.

44. The method as claimed in claim 41, wherein said step (f) comprises the steps of:

(n) delaying the quadrature signal and the in-phase signal by one clock cycle;

(o) subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and

(p) subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

45. The method as claimed in claim 41, wherein the products of said steps (h) and (i) are arithmatically weighted prior to summing in said step (j) such that middle samples of the transmitted signal are given greater weight.

46. The method as claimed in claim 45, wherein eight samples of the transmitted data produce one bit of data.

47. The method as claimed in claim 41, further comprising the steps of:

(n) weighting arithmatically the products of steps (h) and (i);

(o) summing the weight products of said step (n); and

(p) selecting either the sum of said step (j) or said step (o) according to a type of noise or interference present in the transmitted signal;

said step (k) determining a polarity of the selected sum of said step (p).

48. The method as claimed in claim 47, wherein said step (a) comprises the steps of:

(q) Comparing a voltage level of the transmitted Mode S signal with a reference threshold level;

(r) producing a pulse signal when said step (q) determines that the voltage level exceeds the threshold level;

(s) determining if said step (r) has produced two pulses which are separated by a predetermined time gap, thereby detecting a preamble of a Mode S signal when said step (r) has produced two pulses separated by the predetermined time gap.

49. The method as claimed in claim 48, wherein the threshold level is programmable.

50. The method as claimed in claim 47, wherein said step (f) comprises the steps of:

(q) delaying the quadrature signal and the in-phase signal by one clock cycle;

(r) subtracting a current quadrature signal from the current quadrature signal to produce the transformed quadrature signal; and

(s) subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

51. A method for receiving a Mode S signal comprising the steps of:

(a) determining if a Mode S signal is being received;

(b) digitally demodulating the received Mode S signal when said step (a) has determined that the received signal is Mode S;

said step (b) including,

(c) splitting the transmitted Mode S signal into a quadrature signal and an in-phase signal;

(d) performing a digital Hilbert transformation upon the quadrature and in-phase signals;

(e) delaying the transformed quadrature and in-phase signals for one clock cycle;

(f) multiplying the delayed transformed quadrature signal by a current transformed quadrature signal;

(g) multiplying the delayed transformed in-phase signal by a current transformed in-phase signal;

(h) summing the products of said steps (f) and (g);

(i) determining a polarity of the sums of said step (h);

(j) producing data having a logic "1" when said step (i) determines the polarity to be positive; and

(k) producing data having a logic "0" when said step (i) determines the polarity to be negative.

52. The method as claimed in claim 51, wherein said step (a) comprises the steps of:

(l) comparing a voltage level of the transmitted Mode S signal with a threshold level;

(m) producing a pulse signal when said step (l) determines that the voltage level exceeds the threshold level;

(n) determining if said step (m) has produced two pulses which are separated by a predetermined time gap, thereby detecting a preamble of a Mode S signal when said step (m) has produced two pulses separated by the predetermined time gap.

53. The method as claimed in claim 52, wherein the threshold level is programmable.

54. The method as claimed in claim 51, wherein said step (d) comprises the steps of:

(l) delaying the quadrature signal and the in-phase signal by one clock cycle;

(m) subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and

(n) subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

55. The method as claimed in claim 51, wherein the products of said steps (f) and (g) are arithmatically weighted prior to summing in said step (h) such that middle samples of the transmitted signal are given greater weight.

56. The method as claimed in claim 55, wherein eight samples of the transmitted data produce one bit of data.

57. A method for receiving a Mode S signal comprising the steps of:

(a) determining if a Mode S signal is being received;

(b) digitally demodulating the received Mode S signal when said step (a) has determined that the received signal is Mode S;

said step (b) including,

(c) splitting the transmitted Mode S signal into a quadrature signal and an in-phase signal;

(d) performing a digital Hilbert transformation upon the quadrature and in-phase signals;

(e) delaying the transformed quadrature and in-phase signals for one clock cycle;

(f) multiplying the delayed transformed quadrature signal by a current transformed quadrature signal;

(g) multiplying the delayed transformed in-phase signal by a current transformed in-phase signal;

(h) weighting arithmatically the products of said steps (f) and (g);

(i) summing the products of said steps (f) and (g);

(j) summing the weight products of said step (h);

(k) selecting either the sum of said step (i) or the sum of said step (j) according to a type noise or interference present in the transmitted signal;

(l) determining a polarity of the selected sum of said step (k);

(m) producing data having a logic "1" when said step (l) determines the polarity to be positive; and

(n) producing data having a logic "0" when said step (l) determines the polarity to be negative.

58. The method as claimed in claim 57, wherein said step (a) comprises the steps of:

(o) comparing a voltage level of the transmitted Mode S signal with a threshold level;

(p) producing a pulse signal when said step (o) determines that the voltage level exceeds the threshold level;

(q) determining if said step (p) has produced two pulses which are separated by a predetermined time gap, thereby detecting a preamble of a Mode S signal when said step (p) has produced two pulses separated by the predetermined time gap.

59. The method as claimed in claim 58, wherein the threshold level is programmable.

60. The method as claimed in claim 57, wherein said step (d) comprises the steps of:

(o) delaying the quadrature signal and the in-phase signal by one clock cycle;

(p) subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and

(q) subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

61. A method for digitally demodulating an uplink Mode S signal, comprising the steps of:

(a) splitting the uplink Mode S signal into a quadrature signal and an in-phase signal;

(b) performing a digital Hilbert transformation upon the quadrature and in-phase signals;

(c) delaying the transformed quadrature and in-phase signals for one clock cycle;

(d) multiplying the delayed transformed quadrature signal by a current transformed quadrature signal;

(e) multiplying the delayed transformed in-phase signal by a current transformed in-phase signal;

(f) summing the products of said steps (d) and (e);

(g) determining a polarity of the sums of said step (f);

(h) producing data having a logic "1" when said step (g) determines the polarity to be positive; and

(i) producing data having a logic "0" when said step (g) determines the polarity to be negative.

62. The method as claimed in claim 61, wherein said step (b) comprises the steps of:

(j) delaying the quadrature signal and the in-phase signal by one clock cycle;

(k) subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and

(l) subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.

63. The method as claimed in claim 61, wherein the products of said steps (d) and (e) are arithmatically weighted prior to summing in said step (f) such that middle samples of the transmitted signal are given greater weight.

64. The method as claimed in claim 63, wherein eight samples of the transmitted data produce one bit of data.

65. A method for digitally demodulating an uplink Mode S signal, comprising the steps of:

(a) splitting the uplink Mode S signal into a quadrature signal and an in-phase signal;

(b) performing a digital Hilbert transformation upon the quadrature and in-phase signals;

(c) delaying the transformed quadrature and in-phase signals for one clock cycle;

(d) multiplying the delayed transformed quadrature signal by a current transformed quadrature signal;

(e) multiplying the delayed transformed in-phase signal by a current transformed in-phase signal;

(f) weighting arithmatically the products of (d) and (e);

(g) summing the products of said steps (d) and (e);

(h) summing the weighted products of said step (f);

(i) selecting either the sum of said step (g) or the sum of said step (h) according to a type of noise or interference present in the transmitted signal;

(j) determining a polarity of the selected said step (i);

(k) producing data having a logic "1" when said step (j) determines the polarity to be positive; and

(l) producing data having a logic "0" when said step (j) determines the polarity to be negative.

66. The method as claimed in claim 65, wherein said step (b) comprises the steps of:

(m) delaying the quadrature signal and the in-phase signal by one clock cycle;

(n) subtracting a current quadrature signal from the delayed quadrature signal to produce the transformed quadrature signal; and

(o) subtracting a current in-phase signal from the delayed in-phase signal to produce the transformed in-phase signal.