Pressurized interconnection system for semiconductor chips

• US 5,089,880 A
• Filed: 06/07/1989
• Issued: 02/18/1992
• Est. Priority Date: 06/07/1989
• Status: Expired due to Fees

• Current Assignee: Amdahl Corporation (Fujitsu Limited)
• Original Assignee: Amdahl Corporation (Fujitsu Limited)
• Inventors: Meyer, James A., Mikalauskas, Frank, Parks, Howard L.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Le, Hoanganh
• Application Number:
  US07/362,822
• Time in Patent Office: 986 Days
• Field of Search: 357/75, 357/79, 357/74, 357/80, 361/403, 361/414, 361/415, 361/412
• US Class Current: 257/692
• CPC Class Codes: H01L 23/32 Holders for supporting the complete device in operation, i.e. detachable fixtures H01L23/40 takes precedence
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A multilayer pressure stack (microstack) has a plurality of layers formed of a material that may have a high time-dependent deformation factor and a plurality of segments formed in each layer. Each segment comprises a conductive material having a low time-dependent deformation factor and pressure is provided along a column of aligned segments to establish electrical interconnections between the segments in various layers. Interposers formed of non-conductive material may be provided in selected segments to form points of electrical isolation. The plurality of layers, or wafers, includes signal wafers and ground/voltage wafers. The signal wafers are formed of a low dielectric constant material to optimize the propagation velocity of signals traveling in signal traces connecting selected segments in the signal wafer. More than 100 wafers may be provided in a microstack and repairs and revisions of conductor routing are easily accomplished by substituting new wafers within the microstack.

Claims

1. A multilayer pressure stack, (microstack), comprising:

a plurality of layers, each layer comprising a core having first and second surfaces and dielectric layers formed of a material having a high time-dependent deformation factor and provided on said first and second surfaces of said core;

a plurality of segments formed at selected locations in each layer so that each said layer has a segment at each of said selected locations, each segment being formed of a conductive material having a low time-dependent deformation factor and comprising a via provided in the layer and first and second pads overlying said via and corresponding ones of said dielectric layers;

a plurality of bumps provided on selected pads so that one bump is associated with pads of corresponding segments of adjacent ones of said plurality of layers; and

means for aligning said layers so that said segments and bumps form columns and for releasably pressurizing one of said columns.

2. A microstack according to claim 1, further comprising interposers formed of non-conductive material provided in selected segments.

3. A microstack according to claim 2, wherein said plurality of layers comprises signal wafers and ground wafers.

4. A microstack according to claim 3, wherein said core of each said ground wafer comprises a conductive material.

5. A microstack according to claim 3, wherein said core each of said signal wafers comprises a polyamide, and said first and second dielectric layers comprise polytetrafluoroethylene (PTFE).

6. A microstack according to claim 5, wherein:

selected ones of said signal wafers comprise at least one signal trace provided on one of said PTFE layers electrically interconnecting selected segments; and

said signal traces and said columns have a signal propagation velocity greater than 75% of the speed of light.

7. A microstack according to claim 3, further comprising bumps provided on said segments, wherein electrical contact between said segments is provided by said bumps and said means for aligning and releasably pressurizing slightlyd eforms said bumpts to provide planarization of the contacts between adjacent wafers.

8. A microstack according to claim 7, wherein said columns have substantially equal lengths, the lengths being the sum of the lengths of the segments and bumps in each column.

9. A microstack according to claim 2, wherein said plurality of layers comprises signal wafers, ground wafers, and voltage feed wafers.

10. A microstack according to claim 9, wherein each of said layer has a plane, said columns provide interconnections along a z-axis normal to said planes of said layers, and said signal wafers provide electrical interconnections between said columns in planes parallel to said planes of said layers.

11. A microstack according to claim 9, further comprising signal traces provided on said signal wafers, said signal traces being electrically insulated by dielectric materials, including one of said dielectric layers, having a composite dielectric constant of less than 2.

12. A microstack according to claim 11, wherein said core of each said ground wafer comprises a conductive material and said conductive ground planes are electrically isolated from selected ones of said segment.

13. A microstack according to claim 1, wherein selected segments comprise a section formed of non-conductive material and electrically interrupt said columns in which the selected segments are provided.

14. A microstack according to claim 1, wherein selected ones of said segments further comprise interrupts.

15. A microstack according to claim 14, wherein said interrupts comprise a non-conductive material substantially encapsulated in said selected segments.

16. A two-dimensional package for a plurality of semiconductor devices each having an array of contacts, comprising:

first and second semiconductor device support means for supporting first and second groups of the plurality of semiconductor devices so that the contacts of the first group of semiconductor devices face the contacts of the second group of semiconductor devices;

multilayer pressure stack means for electrically interconnecting selected ones of the contacts of the first group of semiconductor devices with selected ones of the contacts of the second group of semiconductor devices, comprising;

a plurality of replaceable layers, each layer having first and second surfaces and comprising a core and a dielectric layer formed of a material ahving a high time-dependent deformation factor,

a plurality of segments formed at selected locations in each layer so that each layer has a segment at each of said selected locations, each segment being formed of a conductive material having a low time-dependent deformation factor and comprising a via provided in the layer and first and second pads overlying the via and corresponding ones of the first and second surfaces of the layer,

a plurality of bumps provided on selected pads so that one bump is associated with pads of corresponding segments of adjacent ones of said plurality of layers, and

interposers formed of non-conductive material provided in selected segments; and

means for aligning said layers so that said segments and said bumps form columns and for releasably pressurizing said columns.

17. A two-dimensional package according to claim 16, wherein said interposers are encapsulated in the conductive material of said segments.

18. A two-dimensional package according to claim 17, wherein said interposers comprise a mateirl having a low time-dependent deformation factor.

19. A two-dimensional package according to claim 16, further comprising signal traces provided on selected dielectric layers and electrically interconnecting selected segments, wherein the effective dielectric constant of the dielectric materials insulating said signal traces is less than 2.

20. A two-dimensional package for a plurality of semiconductor devices each having an array of contacts, comprising:

first means for supporting the semiconductor devices;

second means for electrically interconnecting selected ones of the contacts of the semiconductor devices, comprising;

a plurality of at least fifty replaceable layers, each replaceable layer having first and second surfaces and comprising a core and a dielectric layer formed of a material having a high time-dependent deformation factor,

a plurality of segments formed at selected locations in each layer so that each layer has a segment at each of said selected locations, said selected locations corresponding to the positions of respective ones of the contacts of the semiconductor devices, each segment being formed of a conductive material having a low time-dependent deformation factor and comprising a via provided in the layer and first and second pads overlying the vias and respective ones of the first and second surfaces of the replaceable layer,

a pluraltiy of bumps provided on selected pads so that one bump is associated with pads of corresponding segments of adjacent ones of said plurality of layers, and

signal traces provided on selected layers for providing electrical interconnections between selected ones of said segments, and

interposers formed of non-conductive material provided in selected segments; and

means for aligning said layes so that said segments form columns and for releasably pressurizing said columns of aligned segments and corresponding ones of the contact of the semiconductor devices so that selected ones of said layers may be replaced.

21. A two-dimensional package according to claim 20, wherein said interposers comprise a material having a low time-dependent deformation factor.

22. A two-dimensional package according to claim 20, further comprising signal traces provided on selected signal layes and electrically interconnecting selected segments, wherein the effective dielectric constant of the dielectric materials insulating said signal traces is less than 2.

23. A multilayer pressurized interconnection assembly comprising:

a plurality of signal wafers, each signal wafer comprising a semi-rigid core and a dielectric layer formed of a material having a high time-dependent deformation factor;

signal traces provided on said signal wafers, each said signal trace being surrounded and electrically insulated by dielectric material having a composite dielectric constant of less than 2;

a plurality of ground wafers provided between respective ones of said signal wafers, each said gruond wafer comprising a conductive core and first and second dielectric layers formed of a material having a high time-dependent deformation factor and provided on each side of the conductive core;

a plurality of segments formed at selected locations in each said signal and each said ground wafer so that each signal wafer and each ground wafer has a segment at each of said selected locations, each segment comprising a conductive material having a low time-dependent deformation factor;

interrupt means for selectively, electrically interrupting said segments; and

means for aligning said layers so that said segments form columns, each column having a longitudinal axis, and for releasably pressurizing said columns of aligned segments to allow said microstack to be disassembled and reassembled for replacement of selected ones of said signal wafers.

24. A two-dimensional according to claim 23, wherein said interrupt means comprise interposers encapsulated in selected segments.

25. A two-dimensional according to claim 23, wherein said signal wafers comprise pllytetrafluoroethylene PTFE and said dielectric comprsies PTFE and air.

26. A two-dimensional according to claim 25, wherein the signal propagation veloctiy is greater than 75% of the speed of light.