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Fabrication of a high density stacked gate EPROM split cell with bit line reach-through and interruption immunity

  • US 5,091,327 A
  • Filed: 06/28/1990
  • Issued: 02/25/1992
  • Est. Priority Date: 06/28/1990
  • Status: Expired due to Term
First Claim
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1. A method of fabricating a split-gate memory cell array in a semiconductor substrate of a first conductivity type utilizing stacked etch fabrication techniques, the method comprising the steps of:

  • (a) forming a layer of first dielectric material on the semiconductor substrate;

    (b) forming a layer of first conductive material over the first dielectric material;

    (c) forming a layer of second dielectric material over the first conductive material;

    (d) etching the layer of second dielectric material and the layer of first conductive material to provide a plurality of spaced-apart and parallel-extending floating gate strips of the first conductive material that are separated from the semiconductor substrate by underlying first dielectric material and have second dielectric material formed thereon;

    (e) forming a plurality of dopant regions of a second conductivity type in the semiconductor substrate, adjacent dopant regions being spaced-apart to define a channel region therebetween a first edge of each floating gate strip being used to define an edge of a corresponding dopant region, the floating gate strip extending only over a first section of the channel region defined between the corresponding dopant region and an adjacent dopant region such that a second portion of the channel region is defined between a second edge of the floating gate strip and the adjacent dopant region;

    (f) forming a differential oxide layer on the semiconductor substrate between adjacent floating gate strips, the differential oxide layer comprising simultaneously formed first and second oxide regions, the first oxide region formed over exposed portions of the dopant region and having a first thickness and the second oxide region formed over the second section of the channel region and having a second thickness which is less than the first thickness;

    (g) forming a layer of second conductive material over the differential oxide layer and over the plurality of floating gate strips such that the floating gate strips are separated from the second conductive material by the second dielectric material;

    (h) etching the layer of second conductive material to define a plurality of parallel control gate lines that extend perpendicular to the floating gate strips;

    (i) utilizing the control gate lines as a self-aligned mask in a stacked-etch step to etch the underlying second dielectric material and, subsequently, the underlying floating gate strips to define spaced-apart and parallel-extending floating gates of the split-gate memory cell arraywhereby, during the stacked-etch step, the first oxide region of the differential oxide layer protects the surface of the dopant region and the second oxide region of the differential oxide layer is overetched into the underlying semiconductor substrate to form a trench in the channel region that extends below the junction depth of the dopant region.

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