Fabrication of a high density stacked gate EPROM split cell with bit line reach-through and interruption immunity

• US 5,091,327 A
• Filed: 06/28/1990
• Issued: 02/25/1992
• Est. Priority Date: 06/28/1990
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Bergemont, Albert M.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US07/545,396
• Time in Patent Office: 607 Days
• Field of Search: 437/43, 437/195, 437/49, 437/52, 437/48, 437/979, 357/23.5, 148/DIG. 50, 148/DIG. 163
• US Class Current: 438/261
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

A method for fabricating a split-gate EPROM cell utilizing stacked etch techniques is provided. In accordance with a preferred embodiment of the method, a layer of silicon dioxide is formed on a P- silicon substrate. A layer of polysilicon is formed on the silicon dioxide layer, followed by growth of an oxide/nitride/oxide (ONO) layer. The ONO and polysilicon layers are etched to define floating gates. Next, an edge of each floating gate is utilized in a self-aligned implant of buried N+ bit lines. The floating gate extends only over a first portion of the channel defined between the adjacent buried bit lines. A differential oxide layer is grown on the substrate between adjacent floating gates in a low temperature steam oxidation step. That is, the oxide formed over the exposed portion of the buried N+ bit line is thicker than the oxide formed over the exposed portion of the channel. Following formation of the differential oxide layer, a second layer of polysilicon is formed and etched to define control lines extending perpendicular to the floating gates in the conventional split-gate EPROM cell structure. The control gates are utilized in a stacked etch to complete the split-gate cells. The etch is carried out such that the oxide overlying the N+ bit lines protect the surface of the substrate, avoiding bit line interruption, while the silicon dioxide overlying the exposed portion of the channel is overetched to form a trench into the channel that extends below the junction depth of the N+ region, thereby eliminating bit line to bit line reach-through.

Claims

1. A method of fabricating a split-gate memory cell array in a semiconductor substrate of a first conductivity type utilizing stacked etch fabrication techniques, the method comprising the steps of:

(a) forming a layer of first dielectric material on the semiconductor substrate;

(b) forming a layer of first conductive material over the first dielectric material;

(c) forming a layer of second dielectric material over the first conductive material;

(d) etching the layer of second dielectric material and the layer of first conductive material to provide a plurality of spaced-apart and parallel-extending floating gate strips of the first conductive material that are separated from the semiconductor substrate by underlying first dielectric material and have second dielectric material formed thereon;

(e) forming a plurality of dopant regions of a second conductivity type in the semiconductor substrate, adjacent dopant regions being spaced-apart to define a channel region therebetween a first edge of each floating gate strip being used to define an edge of a corresponding dopant region, the floating gate strip extending only over a first section of the channel region defined between the corresponding dopant region and an adjacent dopant region such that a second portion of the channel region is defined between a second edge of the floating gate strip and the adjacent dopant region;

(f) forming a differential oxide layer on the semiconductor substrate between adjacent floating gate strips, the differential oxide layer comprising simultaneously formed first and second oxide regions, the first oxide region formed over exposed portions of the dopant region and having a first thickness and the second oxide region formed over the second section of the channel region and having a second thickness which is less than the first thickness;

(g) forming a layer of second conductive material over the differential oxide layer and over the plurality of floating gate strips such that the floating gate strips are separated from the second conductive material by the second dielectric material;

(h) etching the layer of second conductive material to define a plurality of parallel control gate lines that extend perpendicular to the floating gate strips;

(i) utilizing the control gate lines as a self-aligned mask in a stacked-etch step to etch the underlying second dielectric material and, subsequently, the underlying floating gate strips to define spaced-apart and parallel-extending floating gates of the split-gate memory cell array

whereby, during the stacked-etch step, the first oxide region of the differential oxide layer protects the surface of the dopant region and the second oxide region of the differential oxide layer is overetched into the underlying semiconductor substrate to form a trench in the channel region that extends below the junction depth of the dopant region.

2. A method of fabricating a split-gate memory cell array in a P-type silicon substrate utilizing stacked etch techniques, the method comprising the steps of:

(a) forming a layer of silicon dioxide on the substrate;

(b) forming a first layer of polysilicon over the layer of silicon dioxide;

(c) forming a layer of ONO over the first layer of polysilicon;

(d) etching the ONO layer and the first layer of polysilicon to define a plurality of spaced-apart and parallel-extending polysilicon floating gate strips that are separated from the substrate by underlying silicon dioxide and have ONO formed thereon;

(e) forming a plurality of N+ regions in the substrate, adjacent N+ regions being spaced-apart to define a substrate channel region therebetween, a first edge of each floating gate strip being used to define an edge of a corresponding N+ region, the floating gate strip extending only over a first portion of the channel region defined between the corresponding N+ region and an adjacent N+ region such that a second section of the channel region is defined between a second edge of the floating gate strip and the adjacent N+ region;

(f) forming a differential oxide layer on the substrate between adjacent floating gate strips, the differential oxide layer comprising simultaneously formed first and second oxide regions, the first oxide region formed over exposed portions of the N+ region and having a first thickness and the second oxide region formed over the second section of the channel region and having a second thickness which is less than the first thickness;

(g) forming a second layer of polysilicon over the differential oxide layer and overlying the plurality of floating ate strips such that the floating gate strips are separated from the second layer of polysilicon by the ONO;

(h) etching the second layer of polysilicon to define a plurality of parallel polysilicon control gate lines that extend perpendicular to the floating gate strips; and

(i) utilizing the polysilicon control gate lines as a self-aligned mask in a stacked-etch step to etch the underlying ONO and, subsequently, the underlying polysilicon floating gate strips to define spaced-apart and parallel-extending polysilicon floating gates of the split-gate memory cell array

whereby, during the stacked-etch step, the first oxide region of the differential oxide layer protects the surface of the N+ regions and the second oxide region of the differential oxide layer is overetched into the underlying P-type substrate to form a trench in the channel region that extends below the junction depth of the N+ regions.

3. A method as in claim 2 and including the further step of forming a p- isolation region in the bottom of the trench.

4. A method as in claim 2 and including the further step of filling the trench.

5. A method as in claim 2 and including the further steps of forming a p- isolation region in the bottom of the trench and filling the trench.