Method of late programming MOS devices
First Claim
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1. A method for late programming integrated circuits, comprising the steps:
- a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with dopant;
b) depositing a first insulating layer, having an upper surface, over said field effect transistor;
c) opening contact windows in said first insulating layer over said source and said drain;
d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain;
e) opening a late programming window in said second level conductive layer over said doped gate; and
f) transporting said dopant from said doped gate into said channel region of said field effect transistor.
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Abstract
Method for late programming of MOS integrated circuit devices. A second or third level conductive layer is used as a device selection mask for transporting dopant from a doped gate (formed from a first level conductive layer) into the channel region of selected field effect transistors.
169 Citations
30 Claims
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1. A method for late programming integrated circuits, comprising the steps:
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a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with dopant; b) depositing a first insulating layer, having an upper surface, over said field effect transistor; c) opening contact windows in said first insulating layer over said source and said drain; d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; e) opening a late programming window in said second level conductive layer over said doped gate; and f) transporting said dopant from said doped gate into said channel region of said field effect transistor. - View Dependent Claims (2, 11, 12, 13, 14, 15)
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3. A method for late programming integrated circuits, comprising the steps:
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a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with dopant; b) depositing a first insulating layer, having an upper surface, over said field effect transistor; c) opening contact windows in said first insulating layer over said source and said drain; d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; e) said second level conductive layer is etched to define source and drain electrodes; f) depositing a second insulating layer, having an upper surface; g) depositing an initial third level conductive layer on said upper surface of said second insulating layer; h) opening a late programming window in said initial third level conductive layer over said doped gate; and i) transporting said dopant from said doped gate into said channel region of said field effect transistor. - View Dependent Claims (4, 5)
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6. A method for late programming integrated circuits, comprising the steps:
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a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer; b) doping said gate with dopant; c) depositing a first insulating layer, having an upper surface, over said field effect transistor; d) opening contact windows in said first insulating layer over said source and said drain; e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; f) opening a late programming window in said second level conductive layer over said doped gate; and g) transporting said dopant from said doped gate into said channel region of said field effect transistor. - View Dependent Claims (7)
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8. A method for late programming integrated circuits, comprising the steps:
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a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer; b) doping said gate with dopant; c) depositing a first insulating layer, having an upper surface, over said field effect transistor; d) opening contact windows in said first insulating layer over said source and said drain; e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; f) said second level conductive layer is etched to define source and drain electrodes; g) depositing a second insulating layer, having an upper surface; h) depositing an initial third level conductive layer on said upper surface of said second insulating layer; i) opening a late programming window in said initial third layer conductive layer over said doped gate; and j) transporting said dopant from said doped, gate into said channel region of said field effect transistor. - View Dependent Claims (9, 10)
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16. A method for late programming integrated circuits, comprising the steps:
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a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with one or more dopants, including a selected dopant; b) depositing a first insulating layer, having an upper surface, over said field effect transistor; c) opening contact windows in said first insulating layer over said source and said drain; d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said t windows to make a low resistance electrical on with said source and said drain; e) opening a late programming window in said second level conductive layer over said doped gate; and f) transporting said selected dopant from said doped gate into said channel region of said field effect transistor. - View Dependent Claims (17, 26, 27, 28, 29, 30)
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18. A method for late programming integrated circuits, comprising the steps:
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a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer that is doped with one or more dopants, including a selected dopant; b) depositing a first insulating layer, having an upper surface, over said field effect transistor; c) opening contact windows in said first insulating layer over said source and said drain; d) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; e) said second level conductive layer is etched to define source and drain electrodes; f) depositing a second insulating layer, having an upper surface; g) depositing an initial third level conductive layer on said upper surface of said second insulating layer; h) opening a late programming window in said initial third level conductive layer over said doped gate; and i) transporting said selected dopant from said doped gate into said channel region of said field effect transistor. - View Dependent Claims (19, 20)
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21. A method for late programming integrated circuits, comprising the steps:
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a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer; b) doping said gate with one or more dopants, including a selected dopant; c) depositing a first insulating layer, having an upper surface, over said field effect transistor; d) opening contact windows in said first insulating layer over said source and said drain; e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; f) opening a late programming window in said second level conductive layer over said doped gate; and g) transporting said selected dopant from said doped gate into said channel region of said field effect transistor. - View Dependent Claims (22)
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23. A method for late programming integrated circuits, comprising the steps:
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a) forming on a silicon wafer, a field effect transistor, having a channel region defined by a source and drain, self-aligned to a gate formed from a first level conductive layer; b) doping said gate with one or more dopants, including a selected dopant; c) depositing a first insulating layer, having an upper surface, over said field effect transistor; d) opening contact windows in said first insulating layer over said source and said drain; e) depositing a second level conductive layer on said upper surface of first insulating layer thereby filling said contact windows to make a low resistance electrical connection with said source and said drain; f) said second level conductive layer is etched to define source and drain electrodes; g) depositing a second insulating layer, having an upper surface; h) depositing an initial third level conductive layer on said upper surface of said second insulating layer; i) opening a late programming window in said initial third layer conductive layer over said doped gate;
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Specification