Semiconductor memory device with a 3-dimensional structure

• US 5,091,762 A
• Filed: 12/14/1990
• Issued: 02/25/1992
• Est. Priority Date: 07/05/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Watanabe, Toshiharu
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Meier, Stephen D.
• Application Number:
  US07/626,404
• Time in Patent Office: 438 Days
• Field of Search: 357/75, 357/23.6, 357/23.7, 357/49, 357/42, 357/55, 357/71
• US Class Current: 257/71
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

A semiconductor memory device comprises a plurality of conductive planar members stacked while being spaced at predetermined distances, a plurality of conductive wires passing through the planar members, and switching elements and capacitance elements. Both types of elements are formed in the vicinity of each of the cross points of the conductive planar members and the wires.

Claims

1. A semiconductor memory apparatus having a semiconductor substrate comprising:

a first block of field-effect-transistor-memory structure on said substrate and a second block of field-effect-transistor memory structure which is directly on said first block; and

a plurality of gate layers serving as word lines, each of which penetrates each of said first and second blocks to intersect said field-effect-transistor memory structures of said first and second blocks,

wherein each of said first block and second block comprises;

a first insulating layer;

a first silicon layer of first conductivity type on said first insulating layer, serving as a source of at least one field-effect transistor and serving as a data line;

a second silicon layer of second conductivity type on said first silicon layer serving a channel of said field-effect transistor;

a third silicon layer of said first conductivity type on said second silicon layer serving a drain of said field-effect transistor;

a second insulating layer on said third silicon layer; and

a first conductive layer on said second insulating layer providing a capacitor between first conductive layer and said third silicon layer.

2. A semiconductor memory apparatus having a semiconductor substrate comprising:

a first block of field-effect-transistor memory structure on said substrate and a second block of field-effect-transistor memory structure which is directly on said first block; and

a plurality of data line layers, each of which penetrates said first and second blocks to intersect said field-effect-transistor memory structures of said first and second blocks;

wherein each of said first block and second block comprises;

a first insulating layer;

a first conductive layer on said first insulating layer, serving as a word line and serving as a gate of at least one field-effect transistor;

a second insulating layer on said first conductive layer;

a first silicon layer of first conductivity type on said second insulating layer serving as a source of said field-effect transistor;

a second silicon layer of second conductivity type on said second insulating layer, said second silicon layer being adjacent to said first silicon layer and serving as a channel of said field-effect transistor;

a third silicon layer of said first conductivity type on said second insulating layer, said third silicon layer being adjacent to said second silicon layer and serving as a drain of said field-effect transistor;

a third insulating layer on said third silicon layer; and

a second conductive layer on said third insulating layer providing a capacitor between said second conductive layer and said third silicon layer.

3. A semiconductor electrically erasable programmable read only memory apparatus having a semiconductor substrate comprising;

a first block of field-effect-transistor memory structure on said substrate and a second block of field-effect-transistor memory structure which is directly on said first block; and

a plurality of gate layers, each of which penetrates said first and second blocks to intersect said field-effect-transistor memory structure of said first and second blocks;

wherein each of said first block and second block comprises;

an insulating layer;

a first silicon layer of first conductivity type on said insulating layer, serving as a source of at least one field-effect transistor;

a second silicon layer of second conductivity type on said first silicon layer, serving as a channel of said transistor;

a third silicon layer of said first conductivity type on said second silicon layer, serving as a drain of said transistor;

a conductive layer on said insulating layer, said conductive layer being near said second silicon layer; and

a second insulating layer separating said conductive layer from said second silicon layer, said conductive layer serving as a floating gate of said transistor.

4. A semiconductor memory apparatus having a semiconductor substrate comprising;

a first block of field-effect-transistor memory structure on said substrate and a second block of field-effect-transistor memory structure which is directly on said first block, each of said first block and second block comprising a plurality of field-effect transistors wherein each of said first block and second block comprises;

a silicon layer; and

a plurality of gate layers, each serving as a word line of said memory apparatus and each of which penetrates said first and second blocks to intersect selected transistors of said field-effect-transistor memory structures of said first and second blocks.