Configuration for testing and burn-in of integrated circuit chips

• US 5,091,769 A
• Filed: 03/27/1991
• Issued: 02/25/1992
• Est. Priority Date: 03/27/1991
• Status: Expired due to Fees

• Current Assignee: Integrated System Assemblies Corp.
• Original Assignee: Integrated System Assemblies Corp.
• Inventors: Eichelberger, Charles W.
• Primary Examiner(s): EPPS, GEORGIA Y
• Application Number:
  US07/676,206
• Time in Patent Office: 335 Days
• Field of Search: 357/72, 357/74, 357/75, 357/80
• US Class Current: 257/687
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

Packaging methods and configurations are disclosed for placing electronic integrated circuit chips into operable chip systems in a manner to facilitate burn-in and testability thereof. The invention addresses the problem of testing bare integrated circuit chips before they are committed to a multichip module. Further, it addresses the problem of burning-in bare chips under biased conditions so that chips with defects therein can be accelerated to failure, thereby avoiding their incorporation into a multichip integrated circuit module. Pursuant to the invention, special connection arrays are disposed in spacer blocks in a predetermined configuration on a substrate. The blocks define areas of the substrate which preferably accommodate a plurality of integrated circuit chips such that each chip is surrounded on each side by a spacer block. One or more connection arrays may be provided in each spacer block. The connection arrays have interconnection pads which in the final structure are accessible to an external probing device. Specific methods of fabrication are also disclosed.

Claims

1. An integrated circuit chip package comprising:

a substrate;

a plurality of integrated circuit chips disposed on said substrate, said integrated circuit chips each having interconnection pads thereon;

a plurality of spacer blocks disposed on said substrate such that each block is located at a side of a chip of said plurality of integrated circuit chips, with at least some of said spacer blocks being disposed between said chips;

at least one of said plurality of blocks including a connection array for applying one of a biasing signal, power signal, ground signal and clock signal to selected chip interconnection pads, said connection array having a plurality of interconnection pads;

an encapsulant surrounding said integrated circuit chips and said spacer blocks, said encapsulant having an upper surface above the tops of the integrated circuit chips and the tops of the spacer blocks and having a plurality of via openings therein, said openings being aligned with at least some of said chip interconnection pads and said connection array interconnection pads; and

a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between at least some of said openings and so as to provide electrical connection to at least some of said chip interconnection pads and said connection array interconnection pads through said openings.

2. The integrated circuit package of claim 1, wherein each of said plurality of spacer blocks disposed about said chips includes a connection array having a plurality of interconnection pads thereon, each array for applying one of a biasing signal, power signal, ground signal and clock signal to selected chip interconnection pads.

3. The integrated circuit package of claim 1, wherein at least one of said spacer blocks disposed about said chips includes multiple connection arrays, each array for applying one of a biasing signal, power signal, ground signal and clock signal to selected chip interconnection pads.

4. The integrated circuit package of claim 1, wherein a plurality of said spacer blocks disposed about said chips include a connection array, at least one of said connection arrays comprising a resistive array for applying a biasing signal to selected chip interconnection pads.

5. The integrated circuit package of claim 1, wherein each of said spacer blocks disposed about said chips includes a resistive array for applying a biasing signal to selected chip interconnection pads.

6. The integrated circuit package of claim 1, wherein said encapsulant, together with said pattern of interconnection conductors disposed thereon, is removable.

7. The integrated circuit package of claim 6, wherein said encapsulant is solvent-sensitive.

8. The integrated circuit package of claim 1, wherein said substrate has a flat upper surface and said encapsulant has an upper surface which is substantially parallel to the upper surface of said substrate.

9. The integrated circuit package of claim 8, wherein the top surfaces of said blocks and the top surfaces of said chips are substantially within a common plane, said plane being parallel to the upper surface of said substrate.

10. The integrated circuit package of claim 1, wherein at least some of said plurality of chips are of different dimensions.

11. The integrated circuit package of claim 10, wherein said spacer blocks are positioned on said substrate in a predetermined pattern.

12. An integrated circuit chip package comprising:

a substrate;

a plurality of spacer blocks disposed on said substrate, said spacer blocks being spaced in a predetermined pattern which frames a multiplicity of distinct areas on said substrate'"'"'s upper surface;

a plurality of integrated circuit chips disposed on said substrate, each of said chips being disposed in one of the substrate areas framed by said spacer blocks such that the chip is bounded on each side by a spacer block, said chips each having interconnection pads thereon;

at least one of said plurality of spacer blocks including a connection array for applying one of a biasing signal, power signal, ground signal and clock signal to selected chip interconnection pads, said connection array having a plurality of interconnection pads thereon;

an encapsulant surrounding said integrated circuit chips and said spacer blocks, said encapsulant having an upper surface above the tops of the integrated circuit chips and the tops of the spacer blocks and having a plurality of via openings therein, said openings being aligned with at least some of said chip interconnection pads and said connection array interconnection pads; and

a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between some of said openings and so as to provide electrical connection to at least between some of said chip interconnection pads and said connection array interconnection pads through said openings.

13. The integrated circuit package of claim 12, wherein each of said plurality of spacer blocks disposed about said chips includes a connection array having a plurality of interconnection pads thereon, each array for applying one of a biasing signal, power signal, ground signal and clock signal to selected chip interconnection pads.

14. The integrated circuit package of claim 12, wherein at least one of said spacer blocks disposed on said chips includes multiple connection arrays, each array for applying one of a biasing signal, power signal, ground signal and clock signal to selected chip interconnection pads.

15. The integrated circuit package of claim 12, wherein a plurality of said spacer blocks disposed about said chips include a connection array which comprises a resistive array for applying a biasing signal to selected chip interconnection pads.

16. An integrated circuit chip package comprising:

a substrate having an upper surface and a lower surface, said upper and lower substrate surfaces being substantially parallel;

at least one integrated circuit chip disposed on the upper surface of said substrate, each integrated circuit chip having interconnection pads thereon;

a solvent sensitive encapsulant surrounding said at least one integrated circuit chip, said encapsulant having an upper surface above the top of said at least one integrated circuit chip and having a plurality of via openings therein, said openings begin aligned with at least some of said chip interconnection pads; and

a pattern of interconnection conductors disposed above the upper surface of said solvent sensitive encapsulant so as to extend through at least some of said openings and so as to provide electrical connection to a least some of said chip interconnection pads.

17. The integrated circuit package of claim 16, further comprising external connect pads disposed above the upper surface of the said solvent sensitive encapsulant, at least some of said external connect pads being electrically connected to said pattern of interconnection conductors for facilitating external electrical connection to at least some of said chip interconnection pads.

18. The integrated circuit package of claim 17, wherein said external connect pads each include an outer surface of oxide-free metal.

19. The integrated circuit package of claim 18, wherein said oxide-free metal comprises gold.

20. The integrated circuit package of claim 16, wherein multiple integrated circuit chips are disposed on said substrate, each of said integrated circuit chips having interconnection pads thereon.

21. The integrated circuit package of claim 20, wherein said pattern of interconnection conductors includes external connect pads disposed above the upper surface of said solvent sensitive encapsulant, said external connect pads being disposed in a preselected pattern.

22. The integrated circuit package of claim 20, wherein at least two of said integrated circuit chips of different size.

23. The integrated circuit package of claim 22, wherein said pattern of interconnection conductors includes external connect pads disposed above the upper surface of said solvent sensitive encapsulant, said external connect pads being disposed in a preselected pattern.

24. The integrated circuit package of claim 16, wherein an adhesive material is disposed between said at least one integrated circuit chip and said substrate for adhesively securing said chip to said substrate, said adhesive material comprising a solvent sensitive material.

25. The integrated circuit package of claim 24, wherein said adhesive material is sensitive to the same solvent as said solvent sensitive encapsulant.

26. The integrated circuit package of claim 24, wherein said adhesive material is sensitive to a different sovlent than said solvent sensitive encapsulant.

27. The integrated circuit package of claim 24, wherein at least one hole is provided in said substrate extending from the lower surface to the upper surface thereof, said at least one hole being positioned under said at least one chip positioned on the upper surface of said substrate.

28. The integrated circuit package of claim 16, wherein a plurality of integrated circuit chips are disposed on the upper surface of said substrate and wherein a plurality of holes are provided in said substrate, each of said holes extending from the lower surface to the upper surface of said substrate, at least some of said plurality of chips being disposed on the upper surface of said substrate at least partially over some of said substrate holes.

29. The integrated circuit package of claim 16, further comprising at least one spacer block disposed on the upper surface of said substrate adjacent said at least one integrated circuit chip.

30. The integrated circuit package of claim 29, wherein a plurality of integrated circuit chips are disposed on the upper surface of said substrate, each of said chips having interconnection pads thereon, and wherein a plurality of spacer blocks are disposed on the upper surface of said substrate, each of said spacer blocks being positioned adjacent one of said integrated circuit chips.

31. The integrated circuit package of claim 30, wherein at least some of said spacer blocks are disposed between said plurality of integrated circuit chips.

32. The integrated circuit package of claim 30, wherein at least one of said plurality of blocks includes a connection array for applying one of a biasing signal, power signal, ground signal and clock signal to selected chip interconnection pads, said connection array having a plurality of interconnection pads, said pattern of interconnection conductors providing electrical connection between at least some of said chip interconnection pads and said connection array interconnection pads.

33. The integrated circuit package of claim 32, wherein said pattern of interconnection conductors includes a plurality of external connect pads disposed above the upper surface of said solvent sensitive encapsulant, said external connect pads being arranged in a preselected pattern.