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Configuration for testing and burn-in of integrated circuit chips

  • US 5,091,769 A
  • Filed: 03/27/1991
  • Issued: 02/25/1992
  • Est. Priority Date: 03/27/1991
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit chip package comprising:

  • a substrate;

    a plurality of integrated circuit chips disposed on said substrate, said integrated circuit chips each having interconnection pads thereon;

    a plurality of spacer blocks disposed on said substrate such that each block is located at a side of a chip of said plurality of integrated circuit chips, with at least some of said spacer blocks being disposed between said chips;

    at least one of said plurality of blocks including a connection array for applying one of a biasing signal, power signal, ground signal and clock signal to selected chip interconnection pads, said connection array having a plurality of interconnection pads;

    an encapsulant surrounding said integrated circuit chips and said spacer blocks, said encapsulant having an upper surface above the tops of the integrated circuit chips and the tops of the spacer blocks and having a plurality of via openings therein, said openings being aligned with at least some of said chip interconnection pads and said connection array interconnection pads; and

    a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between at least some of said openings and so as to provide electrical connection to at least some of said chip interconnection pads and said connection array interconnection pads through said openings.

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